Renesas RL78 Series User Manual page 392

16-bit single-chip microcontrollers
Hide thumbs Also See for RL78 Series:
Table of Contents

Advertisement

RL78/G1D
13.2 Configuration of Serial Array Unit
The serial array unit includes the following hardware.
Item
Shift register
Buffer register
Serial clock I/O
Serial data input
Serial data output
Serial data I/O
Control registers
Notes 1. The number of bits used as the shift register and buffer register differs depending on the unit and channel.
mn = 00, 01: lower 9 bits
2. The lower 8 bits of serial data register mn (SDRmn) can be read or written as the following SFR, depending
on the communication mode.
● CSIp communication ... SIOp (CSIp data register)
● UARTq reception ... RXDq (UARTq receive data register)
● UARTq transmission ... TXDq (UARTq transmit data register)
● IICr communication ... SIOr (IICr data register)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 20, 21),
q: UART number (q = 0, 1), r: IIC number (r = 00, 20)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 13-1. Configuration of Serial Array Unit
Note 1
8 bits or 9 bits
Lower 8 bits or 9 bits of serial data register mn (SDRmn)
SCK00, SCK20 pins (for 3-wire serial I/O), SCL00, SCL20 pins (for simplified I
SI00, SI20 pins (for 3-wire serial I/O), R
SO00, SO20 pins (for 3-wire serial I/O), T
SDA00, SDA20 pins (for simplified I
<Registers of unit setting block>
● Peripheral enable register 0 (PER0)
● Serial clock select register m (SPSm)
● Serial channel enable status register m (SEm)
● Serial channel start register m (SSm)
● Serial channel stop register m (STm)
● Serial output enable register m (SOEm)
● Serial output register m (SOm)
● Serial output level register m (SOLm)
● Serial standby control register m (SSCm)
● Noise filter enable register 0 (NFEN0)
<Registers of each channel>
● Serial data register mn (SDRmn)
● Serial mode register mn (SMRmn)
● Serial communication operation setting register mn (SCRmn)
● Serial status register mn (SSRmn)
● Serial flag clear trigger register mn (SIRmn)
● Port input mode registers 0, 1 (PIM0, PIM1)
● Port output mode registers 0, 1 (POM0, POM1)
● Port mode control register 0 (PMC0)
● Port mode registers 0, 1, 7 (PM0, PM1, PM7)
● Port registers 0, 1, 7 (P0, P1, P7)
CHAPTER 13 SERIAL ARRAY UNIT
Configuration
Notes 1, 2
D0, RxD1 pins (for UART)
X
D0, TxD1 pins (for UART)
X
2
C)
2
C)
371

Advertisement

Table of Contents
loading

This manual is also suitable for:

Rl78/g1dR5f11aggR5f11aghR5f11agj

Table of Contents