Renesas RL78 Series User Manual page 513

RL78/G1D
Caution If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the
PEFm1, FEFm1, or OVFm1 flag is not set and an error interrupt (INTSREq) is not generated.
Therefore, when the setting of SSECm = 1 is made, clear the PEFm1, FEFm1, or OVFm1
flag before setting the SWCm bit to 1 and read the value in SDRm1[7:0] (RxDq register) (8
bits) or SDRm1[8:0] (9 bits).
Remarks 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 13-92 Timing Chart of
2. m = 0; n = 1; q = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1).
CHAPTER 13 SERIAL ARRAY UNIT
492