Renesas RL78 Series User Manual page 777

16-bit single-chip microcontrollers
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RL78/G1D
25.2 Format of User Option Byte
The format of user option byte is shown below.
Note 1
Address: 000C0H/010C0H
7
WDTINIT
WDTINIT
0
1
WINDOW1
0
0
1
1
WDTON
0
1
WDCS2
0
0
0
0
1
1
1
1
WDSTBYON
0
1
Notes 1.
Set the same value as 000C0H to 010C0H when the boot swap operation is used because 000C0H is
replaced by 010C0H.
2.
The window open period is 100% when WDSTBYON = 0, regardless the value of the WINDOW1 and
WINDOW0 bits.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 25-1. Format of User Option Byte (000C0H/010C0H)
6
5
WINDOW1
WINDOW0
Interval interrupt is not used.
Interval interrupt is generated when 75% + 1/2f
WINDOW0
0
Setting prohibited
1
50%
Note 3
0
75%
1
100%
Operation control of watchdog timer counter
Counter operation disabled (counting stopped after reset)
Counter operation enabled (counting started after reset)
WDCS1
WDCS0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Operation control of watchdog timer counter (HALT/STOP mode)
Counter operation stopped in HALT/STOP mode
Counter operation enabled in HALT/STOP mode
4
3
WDTON
WDCS2
Use of interval interrupt of watchdog timer
of the overflow time is reached.
IL
Watchdog timer window open period
Watchdog timer overflow time
(f
= 17.25 kHz (MAX.))
IL
6
2
/f
(3.71 ms)
IL
7
2
/f
(7.42 ms)
IL
8
2
/f
(14.84 ms)
IL
9
2
/f
(29.68 ms)
IL
11
2
/f
(118.72 ms)
IL
13
2
/f
(474.89 ms)
IL
14
2
/f
(949.79 ms)
IL
16
2
/f
(3799.18 ms)
IL
Note 2
CHAPTER 25 OPTION BYTE
2
1
WDCS1
WDCS0
WDSTBYON
Note 2
0
756

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