Renesas RL78 Series User Manual page 477

RL78/G1D
(4) Processing flow (in continuous transmission/reception mode)
Figure 13-68. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode)
<1>
SSmn
STmn
SEmn
SDRmn
Write
SCKp pin
SIp pin
Shift
register mn
SOp pin
INTCSIp
MDmn0
TSFmn
BFFmn
<2> <3>
Note 1
Notes 1. If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn
(SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
2. The transmit data can be read by reading the SDRmn register during this period. At this time, the
transfer operation is not affected.
Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten before
the transfer end interrupt of the last transmit data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 13-69
Transmission/Reception (in Continuous Transmission/Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0), p: CSI number (p = 00, 20), mn = 00, 10
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
(Type 1: DAPmn = 0, CKPmn = 0)
Transmit data 1 Transmit data 2
Write
Receive data 1
Reception & shift operation
Transmit data 1
Data transmission/reception
<2>
Note 2
Receive data 1 Transmit data 3
Write
Read
Receive data 2
Reception & shift operation
Transmit data 2
Data transmission/reception
<3> <4> <2>
Note 2
CHAPTER 13 SERIAL ARRAY UNIT
Receive data 3
Receive data 2
Read
Receive data 3
Reception & shift operation
Transmit data 3
Data transmission/reception
<5>
<3> <4>
Flowchart of Slave
<8>
Read
<6> <7>
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