Renesas RL78 Series User Manual page 687

RL78/G1D
Interrupt
Type
Software
Reset
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 32 indicates the lowest priority.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 18-1.
3. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is set to 1.
4. When the instruction code in FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 18-1. Interrupt Source List (3/3)
Interrupt Source
Name
– BRK Execution of BRK instruction
– RESET RESET pin input
POR Power-on-reset
LVD Voltage detection
WDT Overflow of watchdog timer
TRAP Execution of illegal
Note 4
instruction
IAW Illegal-memory access
RPE RAM parity error
CHAPTER 18 INTERRUPT FUNCTIONS
Internal/
External
Trigger
–
–
Note 3
Vector
Table
Address
007EH (C)
0000H –
666