RL78/G1D
Figure 7-61. Example of Basic Timing of Operation as Delay Counter
TCRmn
TDRmn
INTTMmn
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
TSmn
TEmn
TImn
FFFFH
0000H
a
a+1
2. TSmn: Bit n of timer channel start register m (TSm)
TEmn: Bit n of timer channel enable status register m (TEm)
TImn: TImn pin input signal
TCRmn: Timer count register mn (TCRmn)
TDRmn: Timer data register mn (TDRmn)
CHAPTER 7 TIMER ARRAY UNIT
b
b+1
236