Renesas RL78 Series User Manual page 746

RL78/G1D
Figure 22-6. Timing of Voltage Detector Internal Interrupt Signal Generation
Supply voltage (V
DD
V
LVD
Lower limit of operation voltage
V = 1.51 V (TYP.)
POR
V = 1.50 V (TYP.)
PDR
LVIMK flag
(interrupt MASK)
(set by software)
LVIF flag
LVIMD flag
LVILV flag
INTLVI
LVIIF flag
LVD reset signal
POR reset signal
Internal reset signal
Notes 1. The LVIMK flag is set to "1" by reset signal generation.
2. When the voltage falls, this LSI should be placed in the STOP mode, or placed in the reset state by
controlling the externally input reset signal, before the voltage falls below the operating voltage range
defined in 30.6 AC characteristics. When restarting the operation, make sure that the operation voltage
has returned within the range of operation.
Remark V : POR power supply rise detection voltage
POR
V : POR power supply fall detection voltage
PDR
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
(Option Byte LVIMDS1, LVIMDS0 = 0, 1)
)
Note 1
H
Cleared by
software
H
CHAPTER 22 VOLTAGE DETECTOR
Note 2 Note 2
Time
Cleared
725