Renesas RL78 Series User Manual page 503

RL78/G1D
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
(Selective)
(Essential)
(Essential)
Caution After is set RXEmn bit to 1 of SCRmn register, set the SSmn = 1 from an interval of at least
four clocks of f
Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait
until the transmission target (slave) stops or transmission finishes, and then perform initialization
instead of restarting the transmission.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 13-86. Procedure for Resuming UART Reception
Starting setting for resumption
No
Completing master
preparations?
Yes
Changing setting of the SPSm register
Changing setting of the SDRmn
Changing setting of the SMRmn
and SMRmr registers
Changing setting of the SCRmn register
Clearing error flag
Setting port
Writing to the SSm
register
.
MCK
CHAPTER 13 SERIAL ARRAY UNIT
Stop the target for communication or wait
until completes its communication
operation.
Re-set the register to change the operation
clock setting.
Re-set the register to change the transfer
baud rate setting (setting the transfer clock
by dividing the operation clock (f
Re-set the registers to change serial mode
registers mn, mr (SMRmn, SMRmr)
setting.
Re-set the register to change serial
communication operation setting register
mn (SCRmn) setting.
If the FEF, PEF, and OVF flags remain
set, clear them using serial flag clear
trigger register mn (SIRmn).
Enable data input of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to 1 and set
the SEmn bit to 1 (to enable operation). Become
wait for start bit detection.
)).
MCK
482