Renesas RL78 Series User Manual page 636

RL78/G1D
15.3.9 RF clock generator circuit block
The RF clock generator circuit block generates and outputs a clock signal for supply to the internal circuits of the RF
unit.
This block consists of the RF base clock and RF slow clock generator circuits described below.
(1) RF base clock generator
• XTAL_RF oscillator
This circuit handles the 32-MHz clock signal generated by a 32-MHz resonator connected to the XTAL1_RF and
XTAL2_RF pins. The RF base clock signal is supplied to the entire digital baseband block. An oscillation
stabilization time is required for oscillation to become stable when it is restarted after having been stopped. The
oscillation stabilization time is at least 550 μs, and in general 550 μs + α (where α differs with the oscillator).
(2) RF slow clock generator
<1> On-chip oscillator for the RF slow clock
The RF unit has an on-chip oscillator (f
oscillator is selectable. The signal on the internal EXT32K pin of the RF unit must be driven low to select use
of the internal oscillator. Note that this on-chip oscillator cannot be used for any purpose other than the RF
slow clock.
<2> External input
A square wave externally input to the EXSLK_RF/GPIO3 pin can also provide the RF slow clock (f
32.768 kHz). The signal on the internal EXT32K pin of the RF unit must be driven high to select use of an
external oscillator.
(3) RF base clock output circuit
A clock signal obtained by frequency-dividing the RF base clock can be output from the CLKOUT_RF pin. The
output clock signal can be disabled or set to 16 MHz, 8 MHz, or 4 MHz. This signal can also be used as the
external main system clock of the MCU unit by connecting it to the EXCLK pin. In such cases, this pin and the
EXCLK pin must be connected on the user board.
15.3.10 RF reset circuit block
The RF reset circuit block generates a reset signal to reset the internal circuits of the RF unit. This circuit handles the
following types of reset.
(1) Pin reset
The reset circuit generates a reset signal to reset the RF internal circuit in response of the input of the low level to
RESET_RF.
(2) Wakeup reset
The reset circuit generates a reset signal to reset some of the RF internal circuits when the RF unit wakes up from
the DEEP_SLEEP mode.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
= 32.768 kHz) to produce the RF slow clock. Using or not using this
ILRF
CHAPTER 15 RF TRANSCEIVER
=
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