Renesas RL78 Series User Manual page 258

RL78/G1D
Figure 7-62. Example of Set Contents of Registers to Delay Counter (1/2)
(a) Timer mode register mn (TMRmn)
15 14
TMRmn
CKSmn1 CKSmn0
1/0 1/0
Operation clock (f
(b) Timer output register 0 (TO0)
Bit n
TO0
TO0n
0
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0
TOE0n
0
Note TMRm2, TMRm4, TMRm6:
TMRm1, TMRm3:
TMRm0, TMRm5, TMRm7:
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
13 12 11 10
Note
CCSmn M/S STSmn2 STSmn1
0 0 0/1 0
Setting of MASTERmn bit (channels 2, 4, 6)
0: Independent channel operation function.
Setting of SPLITmn bit (channels 1, 3)
0: 16-bit timer mode
1: 8-bit timer mode.
Count clock selection
0: Selects operation clock (f
) selection
MCK
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
0: Outputs 0 from TO0n.
0: Stops the TO0n output operation by counting operation.
MASTERmn bit
SPLITmn bit
Fixed to 0
9 8 7 6 5
STSmn0 CISmn1 CISmn0
0 1 1/0 1/0 0
Operation mode of channel n
100B: One-count mode
Selection of TImn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
001B: Selects the TImn pin input valid edge.
).
MCK
CHAPTER 7 TIMER ARRAY UNIT
4 3 2 1
MDmn3 MDmn2 MDmn1
0 1 0 0
Start trigger during operation
0: Trigger input is invalid.
1: Trigger input is valid.
0
MDmn0
1/0
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