Renesas RL78 Series User Manual page 243

RL78/G1D
Figure 7-47. Operation Procedure When External Event Counter Function Is Used
TAU
default
setting
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 to CKm3.
Channel Sets the corresponding bit of the noise filter enable
default register 1 (NFEN1) to 0 (off) or 1 (on).
setting
Sets timer mode register mn (TMRmn) (determines
operation mode of channel).
Sets number of counts to timer data register mn
(TDRmn).
Clears the TOE0n bit of timer output enable register 0
(TOE0) to 0.
Operation Sets the TSmn bit to 1.
start The TSmn bit automatically returns to 0 because it is a
trigger bit.
During Set value of the TDRmn register can be changed.
operation The TCRmn register can always be read.
The TSRmn register is not used.
Set values of the TMRmn register, TOM0n, TOL0n,
TO0n, and TOE0n bits cannot be changed.
Operation The TTmn bit is set to 1.
stop The TTmn bit automatically returns to 0 because it is a
trigger bit.
TAU The TAUmEN bit of the PER0 register is cleared to 0.
stop
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Software Operation
CHAPTER 7 TIMER ARRAY UNIT
Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Channel stops operating.
(Clock is supplied and some power is consumed.)
TEmn = 1, and count operation starts.
Value of the TDRmn register is loaded to timer count
register mn (TCRmn) and detection of the TImn pin
input edge is awaited.
Counter (TCRmn) counts down each time input edge of
the TImn pin has been detected. When count value
reaches 0000H, the value of the TDRmn register is loaded
to the TCRmn register again, and the count operation is
continued. By detecting TCRmn = 0000H, the INTTMmn
output is generated.
After that, the above operation is repeated.
TEmn = 0, and count operation stops.
The TCRmn register holds count value and stops.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
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