Renesas RL78 Series User Manual page 681

RL78/G1D
17.6 Cautions on Using DMA Controller
(1) Priority of DMA
During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending
DMA transfer is started after the ongoing DMA transfer is completed. If two or more DMA requests are generated
at the same time, however, their priority is DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3.
If a DMA request and an interrupt request are generated at the same time, the DMA transfer takes precedence,
and then interrupt servicing is executed.
(2) Contention with interrupt requests
During DMA transfer, interrupt requests are held pending even if they are generated. After the DMA transfer in
progress is completed, the pending interrupt request is accepted. At this time, an instruction will not be inserted
between DMA transfer processing and reception of the interrupt request.
If a DMA start request is generated at the time an interrupt request is received, priority is given to the DMA
transfer.
(3) DMA response time
The response time of DMA transfer is as follows.
Response time
Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles.
Cautions 1. The above response time does not include the two clock cycles required for a DMA
Remark
(4) Operation in standby mode
The DMA controller operates as follows in the standby mode.
Status
HALT mode
STOP mode
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 17-3. Response Time of DMA Transfer
3 clocks
transfer.
2. When executing a DMA pending instruction (see 17.6 (4)), the maximum response
time is extended by the execution time of that instruction to be held pending.
3. Do not specify successive transfer triggers for a channel within a period equal to the
maximum response time plus one clock cycle, because they might be ignored.
1 clock: 1/f (f : CPU clock)
CLK CLK
Table 17-4. DMA Operation in Standby Mode
Normal operation
Stops operation.
If DMA transfer conflicts with STOP instruction execution, DMA transfer may be
damaged. Therefore, stop DMA before executing the STOP instruction.
CHAPTER 17 DMA CONTROLLER
Minimum Time
10 clocks
DMA Operation
Maximum Time
Note
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