Renesas RL78 Series User Manual page 377

RL78/G1D
12.7.5 Setting up test mode
Start of setup
PER0 register setting
● ADM0 register setting
● ADM1 register setting
● ADM2 register setting
● ADUL/ADLL register settings
● ADS register setting
● ADTES register setting
(The order of the settings is
irrelevant.)
Reference voltage stabilization
wait time count A
ADCE bit setting
Reference voltage stabilization
wait time count B
ADCS bit setting
Start of A/D conversion
The A/D conversion operations are performed.
End of A/D conversion
Storage of conversion results in
the ADCR and ADCRH registers
Note Depending on the settings of the ADRCK bit and ADUL/ADLL registers, there is a possibility of no interrupt
signal being generated. In this case, the results are not stored in the ADCR and ADCRH registers.
Caution For the procedure for testing the A/D converter, see 23.3.8 A/D test function.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 12-33. Setting up Test Trigger Mode
The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
● ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
ADMD bit: This is used to specify the select mode.
● ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode.
ADSCM bit: This is used to specify the one-shot conversion mode.
● ADM2 register
ADREFP1, ADREFP0, and ADREFM bits:
ADRCK bit: This is used to set the range for the A/D conversion result comparison
value generated by the interrupt signal to AREA2.
ADTYP bit: This is used to specify 10-bit resolution.
● ADUL/ADLL registers
These set ADUL to FFH and ADLL to 00H (initial values).
● ADS register
ADS4 to ADS0 bits: These are used to set to ANI0.
● ADTES register
ADTES1 and ADTES0 bits: AV
The reference voltage stabilization wait time indicated by A below may be required
if the values of the ADREFP1 and ADREFP0 bits are changed.
If the values of ADREFP1 and ADREFP0 are changed to 1 and 0, respectively: A = 5
A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1,
respectively.
The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion
standby status.
The reference voltage stabilization wait time (1
After counting up the reference voltage
register is set (1), and A/D conversion starts.
The A/D conversion end interrupt (INTAD) is generated.
The conversion results are stored in the ADCR and ADCRH registers.
CHAPTER 12 A/D CONVERTER
These are used to select for the reference
voltage.
/AV
REFM REFP
s) is counted by the software.
stabilization wait time B ends, the ADCS bit of the ADM0
Note
s
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