Renesas RL78 Series User Manual page 535

RL78/G1D
(2) Processing flow
SSmn
STmn
SEmn
SOEmn
"H"
TXEmn,
TXEmn = 1 / RXEmn = 0
RXEmn
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
STmn
SEmn
SOEmn
Output is enabled by serial
communication operation
TXEmn,
RXEmn
SDRmn
Dummy data (FFH)
SCLr output
SDAr output
SDAr input D2 D1 D0
Shift
Shi f t operati o n
register mn
INTIICr
TSFmn
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0), r: IIC number (r = 00, 20), mn = 00, 10
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 13-105. Timing Chart of Data Reception
(a) When starting data reception
D7 D6
(b) When receiving last data
Output is stopped by serial communication operation
TXEmn = 0 / RXEmn = 1
Receive data
ACK
D7 D6
CHAPTER 13 SERIAL ARRAY UNIT
TXEmn = 0 / RXEmn = 1
Dummy data (FFH)
D5 D4 D3 D2
Shift operation
Dummy data (FFH)
D5 D4 D3 D2 D1
Shift operation
Reception of last byte
Receive data
ACK
D1 D0
Receive data
NACK
D0
SOmn bit
SOmn bit
manipulation
manipulation
IIC operation stop
CKOmn bit
manipulation
Step condition
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