Renesas RL78 Series User Manual page 31

RL78/G1D
Item
Timer Timer output
RTC output
Clock output/buzzer output
RF unit
(Clock output)
8/10-bit resolution A/D converter
Serial interface
2
I C bus
Multiplier and divider/multiply-
accumulator
DMA controller
Vectored interrupt Internal
sources
External
Reset
Power-on-reset circuit
Voltage detector
On-chip debug function
Power supply voltage
Operating ambient temperature
Package
Notes 1. The number of outputs varies, depending on the setting of channels in use and the number of the master
(see 7.9.3 Operation as multiple PWM output function).
2. When setting to PIOR0 = 1
3. When RF is used, this count includes the pins that connect the MCU with the RF transceiver by the user
externally on the board.
4. The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction
execution not issued by emulation with the on-chip debug emulator.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
R5F11AGG
Note 1
8 channels (PWM outputs: 7
1 channel
1 Hz (subsystem clock: f = 32.768 kHz)
SUB
Note 3
1
● 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: f = 20 MHz operation)
MAIN
● 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: f = 32.768 kHz operation)
SUB
● 16 MHz, 8 MHz, 4 MHz
8 channels
2
● CSI/simplified I C/UART: 1 channel
2
● CSI/simplified I C: 1 channel
● UART: 1 channel
● CSI: 1 channel (dedicated for internal communications)
1 channel
Multiplication: 16 bits × 16 bits = 32 bits (Unsigned or signed)
Division: 32 bits ÷ 32 bits = 32 bits (Unsigned)
Multiply-accumulate: 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
4 channels
29
4
● Reset by RESET pin
● Internal reset by watchdog timer
● Internal reset by power-on-reset
● Internal reset by voltage detector
● Internal reset by illegal instruction execution
● Internal reset by RAM parity error
● Internal reset by illegal-memory access
● Power-on-reset: 1.51 (TYP.)
● Power-down-reset: 1.50 (TYP.)
● Rising edge : 1.67 V to 3.13 V (12 stages)
● Falling edge : 1.63 V to 3.06 V (12 stages)
Provided
V = 1.6 to 3.6 V (V =1.8 to 3.6 V on usage of DC-DC converter)
DD DD
T = -40 to +85 °C
A
48-pin QFN (6 × 6), (0.4 mm pitch)
R5F11AGH
Note 2
)
Note 4
CHAPTER 1 OUTLINE
(2/2)
R5F11AGJ
10