Renesas RL78 Series User Manual page 668

RL78/G1D
Address: F020AH (DMC2), F020BH (DMC3)
Symbol <7>
DMCn STGn
(When n = 2 or 3)
IFCn IFCn
3 2
0 0
0 0
1 0
1 0
1 0
1 0
Other than above
Note The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values.
Remark n: DMA channel number (n = 2, 3)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 17-4. Format of DMA Mode Control Register n (DMCn) (3/3)
After reset: 00H
<6> <5>
DRSn DSn
IFCn IFCn
1 0
Trigger signal
0 0 –
0 1 INTAD
0 0 INTST1
0 1 INTSR1
1 0 INTCSI20
1 1 INTCSI21
Setting prohibited
CHAPTER 17 DMA CONTROLLER
R/W
<4> 3
DWAITn IFCn3
Selection of DMA start source
Disables DMA transfer by interrupt.
(Only software trigger is enabled.)
A/D conversion end interrupt
UART1 transmission transfer end or buffer empty interrupt
UART1 reception transfer end interrupt
CSI20 transfer end or buffer empty interrupt
CSI21 transfer end or buffer empty interrupt
2 1
IFCn2 IFCn1
Note
Trigger contents
0
IFCn0
647