Renesas RL78 Series User Manual page 714

RL78/G1D
(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
(a) When high-speed on-chip oscillator clock is used as CPU clock
Reset signal
Status of CPU
High-speed on-chip
oscillator clock
Reset signal
Status of CPU
High-speed
system clock
(X1 oscillation)
Note For the reset processing time, see CHAPTER 20 RESET FUNCTION.
For the reset processing time of the power-on-reset circuit (POR) and voltage detector (LVD), see
CHAPTER 21 POWER-ON-RESET CIRCUIT.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 19-2. HALT Mode Release by Reset (1/2)
HALT
instruction
Normal operation
(high-speed on-chip
oscillator clock) HALT mode
Oscillates
(b) When high-speed system clock is used as CPU clock
HALT
instruction
Normal operation
(high-speed
system clock)
HALT mode
Oscillates
CHAPTER 19 STANDBY FUNCTION
Normal operation
Reset (high-speed on-chip
Note
period oscillator clock)
Oscillation
stopped
Oscillates
Wait for oscillation
accuracy stabilization
Normal operation
Reset (high-speed on-chip
Note
oscillator clock)
period
Oscillation Oscillation
stopped stopped
Oscillates
Oscillation stabilization time
(check by using OSTC register)
Starting X1 oscillation is
specified by software.
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