Renesas RL78 Series User Manual page 402

16-bit single-chip microcontrollers
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RL78/G1D
Figure 13-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2)
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03),
F0158H, F0159H (SCR10), F015AH, F015BH (SMR11)
Symbol
15
14
SCRmn
TXE
RXE
mn
mn
TXEmn
0
0
1
1
DAPmn
0
0
1
1
Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode and simplified I
EOCmn
0
1
Set EOCmn = 0 in the CSI mode, simplified I
Notes 1. The SCR00 and SCR02 registers only.
2. The SCR00 and SCR01 registers only. Others are fixed to 1.
3. When using CSImn not with EOCmn = 0, error interrupt INTSREn may be generated.
Caution Be sure to clear bits 3, 6, and 11 to "0" (Also clear bit 5 of the SCR01, SCR03, SCR10, or SCR11
register to 0). Be sure to set bit 2 to "1".
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3 for m = 0, n = 0, 1 for m = 1)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
13
12
11
10
DAP
CKP
0
EOC
mn
mn
mn
RXEmn
0
Disable communication.
1
Reception only
0
Transmission only
1
Transmission/reception
CKPmn
Selection of data and clock phase in CSI mode
SCKp
0
SOp
SI p input timing
SCKp
1
SOp
SI p input timing
SCKp
0
SOp
SI p input timing
SCKp
1
SOp
SI p input timing
Selection of masking of error interrupt signal (INTSREx (x = 0 to 3))
Disables generation of error interrupt INTSREx (INTSRx is generated).
Enables generation of error interrupt INTSREx (INTSRx is not generated if an error occurs).
CHAPTER 13 SERIAL ARRAY UNIT
After reset: 0087H
9
8
7
6
PTC
PTC
DIR
0
mn1
mn0
mn
n1
Setting of operation mode of channel n
D7 D6 D5
D4 D3 D2 D1 D0
D7
D6 D5 D4
D7
D6
D5
D4
D3
D7 D6 D5
D4 D3 D2
2
2
C mode, and during UART transmission
R/W
5
4
3
2
SLCm
SLC
0
1
Note 1
mn0
D3 D2 D1 D0
D2
D1
D0
D1 D0
C mode.
Note 3
.
1
0
DLSm
DLS
Note 2
n1
mn0
Type
1
2
3
4
381

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