Renesas RL78 Series User Manual page 280

16-bit single-chip microcontrollers
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RL78/G1D
When Multiple PWM Output Function (Slave Channel) Is Used (output two types of PWMs)
(a) Timer mode register mp, mq (TMRmp, TMRmq)
15
14
TMRmp
CKSmp1
CKSmp0
1/0
0
15
14
TMRmq
CKSmq1
CKSmq0
1/0
0
Operation clock (f
00B: Selects CKm0 as operation clock of channel p, q.
10B: Selects CKm1 as operation clock of channel p, q.
(b) Timer output register 0 (TO0)
Bit q
Bit p
TO0
TO0q
TO0p
1/0
1/0
(c) Timer output enable register 0 (TOE0)
Bit q
Bit p
TOE0
TOE0q
TOE0p
1/0
1/0
(d) Timer output level register 0 (TOL0)
Bit q
Bit p
TOL0
TOL0q
TOL0p
1/0
1/0
(e) Timer output mode register 0 (TOM0)
Bit q
Bit p
TOM0
TOM0q
TOM0p
1
1
Note TMRm2, TMRm4, TMRm6: MASTERmp, MASTERmq bit
TMRm1, TMRm3:
TMRm5, TMRm7:
Remark
m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4)
p: Slave channel number 1, q: Slave channel number 2
n < p < q
7 (Where p and q are integers greater than n)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 7-77. Example of Set Contents of Registers
13
12
11
10
Note
CCSmp
M/S
STSmp2
STSmp1
0
0
0
1
13
12
11
10
Note
CCSmq
STSmq2
STSmq1
M/S
0
0
0
1
Setting of MASTERmp, MASTERmq bits (channels 2, 4, 6)
0: Independent channel operation function.
Setting of SPLITmp, SPLITmq bits (channels 1, 3)
1: 16-bit timer mode.
Count clock selection
0: Selects operation clock (f
) selection
MCK
* Make the same setting as master channel.
0: Outputs 0 from TO0p or TO0q.
1: Outputs 1 from TO0p or TO0q.
0: Stops the TO0p or TO0q output operation by counting operation.
1: Enables the TO0p or TO0q output operation by counting operation.
0: Positive logic output (active-high)
1: Negative logic output (active-low)
1: Sets the slave channel output mode.
SPLITmp, SPLITmq bit
Fixed to 0
9
8
7
6
5
STSmp0
CISmp1
CISmp0
0
0
0
0
0
9
8
7
6
5
STSmq0
CISmq1
CISmq0
0
0
0
0
0
Operation mode of channel p, q
100B: One-count mode
Selection of TImp and TImq pins input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
).
MCK
CHAPTER 7 TIMER ARRAY UNIT
4
3
2
1
MDmp3
MDmp2
MDmp1
0
1
0
0
4
3
2
1
MDmq3
MDmq2
MDmq1
0
1
0
0
Start trigger during operation
1: Trigger input is valid.
0
MDmp0
1
0
MDmq0
1
259

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