Renesas RL78 Series User Manual page 562

RL78/G1D
14.4.2 Setting transfer clock by using IICWLn and IICWHn registers
(1) Setting transfer clock on master side
Transfer clock =
At this time, the optimal setting values of the IICWLn and IICWHn registers are as follows.
(The fractional parts of all setting values are rounded up.)
● When the fast mode
IICWLn = Transfer clock × f
IICWHn = ( Transfer clock – t
● When the normal mode
IICWLn = Transfer clock × f
Transfer clock – t
IICWHn = (
● When the fast mode plus
IICWLn = Transfer clock × f
IICWHn = ( Transfer clock – t
(2) Setting IICWLn and IICWHn registers on slave side
(The fractional parts of all setting values are truncated.)
● When the fast mode
IICWLn = 1.3 µs × f
IICWHn = (1.2 µs – t
● When the normal mode
IICWLn = 4.7 µs × f
IICWHn = (5.3 µs – t
● When the fast mode plus
IICWLn = 0.50 µs × f
IICWHn = (0.50 µs – t
(Caution and Remarks are listed on the next page.)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
f
MCK
IICWL + IICWH + f (t + t
MCK R
0.52
MCK
0.48
– t ) × f
R F MCK
0.47
MCK
0.53
– t ) × f
R F MCK
0.50
MCK
0.50
– t ) × f
R F MCK
MCK
– t ) × f
R F MCK
MCK
– t ) × f
R F MCK
MCK
– t ) × f
R F MCK
CHAPTER 14 SERIAL INTERFACE IICA
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F
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