Renesas RL78 Series User Manual page 544

RL78/G1D
14.2 Configuration of Serial Interface IICA
Serial interface IICA includes the following hardware.
Item
Registers
Control registers
Remark n = 0
(1) IICA shift register n (IICAn)
The IICAn register is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the
serial clock. The IICAn register can be used for both transmission and reception.
The actual transmit and receive operations can be controlled by writing and reading operations to the IICAn register.
Cancel the wait state and start data transfer by writing data to the IICAn register during the wait period.
The IICAn register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears IICAn to 00H.
Address: FFF50H (IICA0), FFF54H (IICA1)
Symbol
IICAn
Cautions 1. Do not write data to the IICAn register during data transfer.
2. Write or read the IICAn register only during the wait period. Accessing the IICAn register in a
communication state other than during the wait period is prohibited. When the device serves
as the master, however, the IICAn register can be written only once after the communication
trigger bit (STTn) is set to 1.
3. When communication is reserved, write data to the IICAn register after the interrupt triggered
by a stop condition is detected.
Remark n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 14-1. Configuration of Serial Interface IICA
IICA shift register n (IICAn)
Slave address register n (SVAn)
Peripheral enable register 0 (PER0)
IICA control register n0 (IICCTLn0)
IICA status register n (IICSn)
IICA flag register n (IICFn)
IICA control register n1 (IICCTLn1)
IICA low-level width setting register n (IICWLn)
IICA high-level width setting register n (IICWHn)
Port mode register 6 (PM6)
Port register 6 (P6)
Figure 14-3. Format of IICA Shift Register n (IICA)
7 6 5
CHAPTER 14 SERIAL INTERFACE IICA
Configuration
After reset: 00H R/W
4 3 2 1 0
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