Renesas RL78 Series User Manual page 545

RL78/G1D
(2) Slave address register n (SVAn)
This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode.
The SVAn register can be set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STDn = 1 (while the start condition is detected).
Reset signal generation clears the SVAn register to 00H.
Address: F0234H (SVA0), F023DH (SVA1)
Symbol
SVAn
Note Bit 0 is fixed to 0.
(3) SO latch
The SO latch is used to retain the SDAAn pin's output level.
(4) Wakeup controller
This circuit generates an interrupt request (INTIICAn) when the address received by this register matches the address
value set to the slave address register n (SVAn) or when an extension code is received.
(5) Serial clock counter
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify
that 8-bit data was transmitted or received.
(6) Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIICAn).
2
An I C interrupt request is generated by the following two triggers.
• Falling edge of eighth or ninth clock of the serial clock (set by the WTIMn bit)
• Interrupt request generated when a stop condition is detected (set by the SPIEn bit)
Remark WTIMn bit: Bit 3 of IICA control register n0 (IICCTLn0)
SPIEn bit: Bit 4 of IICA control register n0 (IICCTLn0)
(7) Serial clock controller
In master mode, this circuit generates the clock output via the SCLAn pin from a sampling clock.
(8) Serial clock wait controller
This circuit controls the wait timing.
(9) ACK generator, stop condition detector, start condition detector, and ACK detector
These circuits generate and detect each status.
(10) Data hold time correction circuit
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
Remark n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-4. Format of Slave Address Register n (SVAn)
7 6 5
A6 A5 A4
CHAPTER 14 SERIAL INTERFACE IICA
After reset: 00H R/W
4 3 2
A3 A2 A1
1 0
Note
A0 0
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