Renesas RL78 Series User Manual page 758

RL78/G1D
23.3.1.2 Flash memory CRC operation result register (PGCRCL)
This register is used to store the high-speed CRC operation results.
The PGCRCL register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 23-2. Format of Flash Memory CRC Operation Result Register (PGCRCL)
Address: F02F2H After reset: 0000H
Symbol 15
PGCRCL PGCRC15
7
PGCRC7
PGCRC15 to PGCRC0
0000H to FFFFH
Caution The PGCRCL register can only be written if CRC0EN (bit 7 of the CRC0CTL register) = 1.
Figure 23-3 shows the flowchart of flash memory CRC operation function (high-speed CRC).
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
R/W
14 13
PGCRC14 PGCRC13
6 5
PGCRC6 PGCRC5
Store the high-speed CRC operation results.
CHAPTER 23 SAFETY FUNCTIONS
12 11
PGCRC12 PGCRC11
4 3
PGCRC4 PGCRC3
High-speed CRC operation results
10 9
PGCRC10 PGCRC9
2 1
PGCRC2 PGCRC1
8
PGCRC8
0
PGCRC0
737