Renesas RL78 Series User Manual page 537

RL78/G1D
13.7.4 Stop condition generation
After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released.
(1) Processing flow
STmn
SEmn
SOEmn
Note
SCLr output
SDAr output
Note During a receive operation, the SOEmn bit of serial output enable register m (SOEm) is cleared to 0 before
receiving the last data.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 13-107. Timing Chart of Stop Condition Generation
SOmn
Operation
bit manipulation
stop
Figure 13-108. Flowchart of Stop Condition Generation
Completion of data
transmission/data reception
Starting generation of stop condition.
Writing 1 to the STmn bit to clear
(the SEmn bit is cleared to 0)
Writing 0 to the SOEmn bit
Writing 0 to the SOmn bit
Writing 1 to the CKOmn bit
Wait
Writing 1 to the SOmn bit
End of IIC communication
CHAPTER 13 SERIAL ARRAY UNIT
CKOmn SOmn
bit manipulation bit manipulation
Stop condition
Operation stop status (operable CKOmn
manipulation)
Operation disable status (operable SOmn
manipulation)
Timing to satisfy the low width standard of SCL
2
for the I C bus.
Secure a wait time so that the specifications of
2
I C on the slave side are satisfied.
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