Renesas RL78 Series User Manual page 409

RL78/G1D
13.3.8 Serial channel start register m (SSm)
The SSm register is a trigger register that is used to enable starting communication/count by each channel.
When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m
(SEm) is set to 1 (Operation is enabled). Because the SSmn bit is a trigger bit, it is cleared immediately when SEmn = 1.
The SSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSm register can be set with an 1-bit or 8-bit memory manipulation instruction with SSmL.
Reset signal generation clears the SSm register to 0000H.
Address: F0122H, F0123H (SS0)
Symbol 15 14
SS0 0 0
Address: F0162H, F0163H (SS1)
Symbol 15 14
SS1 0 0
SSmn
0 No trigger operation
1 Sets the SEmn bit to 1 and enters the communication wait status
Note If set the SSmn = 1 to during a communication operation, will wait status to stop the communication.
At this time, holding status value of control register and shift register, SCKmn and SOmn pins, and FEFmn,
PEFmn, OVFmn flags.
Cautions 1. Be sure to clear bits 15 to 4 of the SS0 register and bits 15 to 2 of the SS1 register to "0".
2. For the UART reception, set the RXEmn bit of SCRmn register to 1, and then be sure to set
SSmn to 1 after 4 or more f
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3 for m = 0, n = 0, 1 for m = 1)
2. When the SSm register is read, 0000H is always read.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 13-12. Format of Serial Channel Start Register m (SSm)
After reset: 0000H R/W
13 12 11 10
0 0 0 0
After reset: 0000H R/W
13 12 11 10
0 0 0 0
MCK
9 8 7 6
0 0 0 0
9 8 7 6
0 0 0 0
Operation start trigger of channel n
Note
clocks have elapsed.
CHAPTER 13 SERIAL ARRAY UNIT
5 4 3 2
0 0 SS03 SS02 SS01 SS00
5 4 3 2
0 0 0 0
.
1 0
1 0
SS11 SS10
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