Renesas RL78 Series User Manual page 146

RL78/G1D
Figure 6-6. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFA3H
Symbol 7
OSTS 0
OSTS2
0
0
0
0
1
1
1
1
Cautions 1. Change the setting of the OSTS register before setting the MSTOP bit of the clock
Remark f
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
After reset: 07H R/W
6 5
0 0
OSTS1 OSTS0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
operation status control register (CSC) to 0.
2. The oscillation stabilization time counter counts up to the oscillation stabilization
time set by the OSTS register.
In the following cases, set the oscillation stabilization time of the OSTS register to
the value greater than the count value which is to be checked by the OSTC register
after the oscillation starts.
● If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or
subsystem clock is being used as the CPU clock.
● If the STOP mode is entered and then released while the high-speed on-chip
oscillator clock is being used as the CPU clock with the X1 clock oscillating. (Note,
therefore, that only the status up to the oscillation stabilization time set by the
OSTS register is set to the OSTC register after the STOP mode is released.)
3. The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts ("a" below).
STOP mode release
X1 pin voltage
waveform
: X1 clock oscillation frequency
X
CHAPTER 6 CLOCK GENERATOR
4 3
0 0
Oscillation stabilization time selection
f
X
8
2 /f 25.6 µs
X
9
2 /f 51.2 µs
X
10
2 /f 102 µs
X
11
2 /f 204 µs
X
13
2 /f 819 µs
X
15
2 /f 3.27 ms
X
17
2 /f 13.1 ms
X
18
2 /f 26.2 ms
X
a
2 1
OSTS2 OSTS1 OSTS0
= 10 MHz f = 20 MHz
X
12.8 µs
25.6 µs
51.2 µs
102 µs
409 µs
1.63 ms
6.55 ms
13.1 ms
0
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