Renesas RL78 Series User Manual page 751

RL78/G1D
Notes 1. The LVIMK flag is set to "1" by reset signal generation.
2. After an interrupt is generated, perform the processing according to Figure 22-8 Processing Procedure
After an Interrupt Is Generated.
3. After a reset is released, perform the processing according to Figure 22-9 Initial Setting of Interrupt and
Reset Mode.
Remark V : POR power supply rise detection voltage
POR
V : POR power supply fall detection voltage
PDR
Internal reset by LVD
is generated
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 22-8. Processing Procedure After an Interrupt Is Generated
INTLVI generated
Save processing
LVISEN = 1
LVILV = 0
LVISEN = 0
No
LVIOMSK = 0
Yes
LVD reset generated
LVISEN = 1
LVIMD = 0
LVISEN = 0
Normal operation
CHAPTER 22 VOLTAGE DETECTOR
Perform required save processing.
Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1).
Set the LVILV bit to 0 to set the high-voltage
detection level (V ).
LVDH
Set the LVISEN bit to 0 to enable voltage
detection.
Yes
When an internal reset by voltage detector (LVD)
is not generated, a condition of V
No
Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1)
Set the LVIMD bit to 0 to set interrupt mode.
Set the LVISEN bit to 0 to enable voltage
detection.
becomes V ≥ V .
DD DD LVDH
730