Renesas RL78 Series User Manual page 552

RL78/G1D
Note
SPTn
0 Stop condition is not generated.
1 Stop condition is generated (termination of master device's transfer).
Cautions concerning set timing
● For master reception:
● For master transmission: A stop condition cannot be generated normally during the acknowledge period.
● Cannot be set to 1 at the same time as start condition trigger (STTn).
● The SPTn bit can be set to 1 only when in master mode.
● When the WTIMn bit has been cleared to 0, if the SPTn bit is set to 1 during the wait period that follows output of
eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. The WTIMn
bit should be changed from 0 to 1 during the wait period following the output of eight clocks, and the SPTn bit should
be set to 1 during the wait period that follows the output of the ninth clock.
● Once SPTn is set (1), setting it again (1) before the clear condition is met is not allowed.
Condition for clearing (SPTn = 0)
● Cleared by loss in arbitration
● Automatically cleared after stop condition is detected
● Cleared by LRELn = 1 (exit from communications)
● When IICEn = 0 (operation stop)
● Reset
Note When the SPTn register is read, 0 is always read.
Caution When bit 3 (TRCn) of the IICA status register n (IICSn) is set to 1 (transmission status), bit 5
(WRELn) of IICA control register n0 (IICCTLn0) is set to 1 during the ninth clock and wait is
canceled, after which the TRCn bit is cleared (reception status) and the SDAAn line is set to
high impedance. Release the wait performed while the TRCn bit is 1 (transmission status)
by writing to the IICA shift register n.
Remarks 1. Bit 0 (SPTn) becomes 0 when it is read after data setting.
2. n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-6. Format of IICA Control Register n0 (IICCTLn0) (4/4)
Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when the ACKEn bit has been cleared to 0 and
slave has been notified of final reception.
Therefore, set it during the wait period that follows output of the ninth clock.
CHAPTER 14 SERIAL INTERFACE IICA
Stop condition trigger
Condition for setting (SPTn = 1)
● Set by instruction
531