Renesas RL78 Series User Manual page 882

RL78/G1D
2
(3) I C fast mode plus
(T = –40 to +85°C, 2.7 V ≤ V
A
Parameter
SCLA0 clock frequency
Setup time of restart
condition
Note 1
Hold time
Hold time when SCLA0 =
"L"
Hold time when SCLA0 =
"H"
Data setup time
(reception)
Data hold time
Note 2
(transmission)
Setup time of stop
condition
Bus-free time
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of t
(acknowledge) timing.
Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (I
the redirect destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Fast mode plus: C
SCLAn
SDAAn
t
BUF
Stop Start
condition condition
Remark n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
= V = AV
DD DD_RF DD_RF
Symbol Conditions
Fast mode plus:
f 2.7 V ≤ V
SCL
f ≥ 10 MHz
CLK
t 2.7 V ≤ V ≤ 3.6 V
SU:STA DD
t 2.7 V ≤ V ≤ 3.6 V
HD:STA DD
t 2.7 V ≤ V ≤ 3.6 V
LOW DD
t 2.7 V ≤ V ≤ 3.6 V
HIGH DD
t 2.7 V ≤ V ≤ 3.6 V
SU:DAT DD
t 2.7 V ≤ V ≤ 3.6 V
HD:DAT DD
t 2.7 V ≤ V ≤ 3.6 V
SU:STO DD
t 2.7 V ≤ V ≤ 3.6 V
BUF DD
HD:DAT
= 120 pF, R = 1.1 kΩ
b b
IICA serial transfer timing
t t
LOW R
t
t
HD:DAT
HIGH
t
HD:STA
CHAPTER 30 ELECTRICAL SPECIFICATIONS
≤ 3.6 V, V = V = AV
SS SS_RF
HS (high-speed
main) Mode
MIN.
≤ 3.6 V 0
DD
0.26
0.26
0.5
0.26
50
0
0.26
0.5
is during normal transfer and a wait state is inserted in the ACK
, I
OH1
t
t
F
SU:STA
t
SU:DAT
Restart
condition
= 0 V)
SS_RF
LS (low-speed LV (low-voltage
main) Mode
MAX. MIN. MAX. MIN.
1000 –
–
–
–
–
–
0.45 –
–
–
, V , V ) must satisfy the values in
OL1 OH1 OL1
t
HD:STA
Unit
main) Mode
MAX.
– kHz
– µs
– µs
– µs
– µs
– µs
– µs
– µs
– µs
t
SU:STO
Stop
condition
861