Renesas RL78/G13 User Manual
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Renesas RL78/G13 User Manual

16-bit single-chip microcontrollers
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RL78/G13
16
16-Bit Single-Chip Microcontrollers
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
User's Manual: Hardware
Rev.1.00 Sep 2011

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Summary of Contents for Renesas RL78/G13

  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
  • Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
  • Page 3 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
  • Page 4 This manual is intended to give users an understanding of the functions described in the Organization below. Organization The RL78/G13 manual is separated into two parts: this manual and the instructions edition (common to the RL78 Microcontroller). RL78/G13 RL78 Microcontroller User’s Manual...
  • Page 5 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. RL78/G13 User’s Manual Hardware This manual RL78 Microcontroller Instructions User’s Manual R01US0015E Documents Related to Flash Memory Programming Document Name Document No.
  • Page 6 Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual” website (http://www.renesas.com/prod/package/manual/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing.

  • Page 7: Table Of Contents

    CONTENTS CHAPTER 1 OUTLINE..........................1 1.1 Features............................1 1.2 Ordering Information........................3 1.3 Pin Configuration (Top View) ......................6 1.3.1 20-pin products........................... 6 1.3.2 24-pin products........................... 7 1.3.3 25-pin products........................... 8 1.3.4 30-pin products........................... 9 1.3.5 32-pin products..........................10 1.3.6 36-pin products..........................11 1.3.7 40-pin products..........................
  • Page 8 CHAPTER 2 PIN FUNCTIONS ....................... 44 2.1 Pin Function List .......................... 44 2.1.1 20-pin products..........................45 2.1.2 24-pin products..........................46 2.1.3 25-pin products..........................47 2.1.4 30-pin products..........................48 2.1.5 32-pin products..........................50 2.1.6 36-pin products..........................52 2.1.7 40-pin products..........................54 2.1.8 44-pin products..........................
  • Page 9 CHAPTER 3 CPU ARCHITECTURE ...................... 98 3.1 Memory Space ..........................98 3.1.1 Internal program memory space..................... 114 3.1.2 Mirror area............................117 3.1.3 Internal data memory space ......................119 3.1.4 Special function register (SFR) area ....................120 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ..... 120 3.1.6 Data memory addressing .......................
  • Page 10 4.2.8 Port 7.............................. 211 4.2.9 Port 8.............................. 218 4.2.10 Port 9............................222 4.2.11 Port 10............................227 4.2.12 Port 11............................231 4.2.13 Port 12............................234 4.2.14 Port 13............................239 4.2.15 Port 14............................241 4.2.16 Port 15............................249 4.3 Registers Controlling Port Function ..................251 4.4 Port Function Operations ......................
  • Page 11 6.1.1 Independent channel operation function ..................324 6.1.2 Simultaneous channel operation function..................325 6.1.3 8-bit timer operation function (channels 1 and 3 only)..............326 6.1.4 LIN-bus supporting function (channel 7 of unit 0 only) ..............327 6.2 Configuration of Timer Array Unit .................... 328 6.3 Registers Controlling Timer Array Unit..................
  • Page 12 7.4.5 1 Hz output of real-time clock ......................453 7.4.6 Example of watch error correction of real-time clock ..............454 CHAPTER 8 INTERVAL TIMER ......................457 8.1 Functions of Interval Timer ....................... 457 8.2 Configuration of Interval Timer....................457 8.3 Registers Controlling Interval Timer ..................458 8.4 Interval Timer Operation ......................
  • Page 13 11.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) ........514 11.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) ........515 11.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode)........516 11.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) ........517 11.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) ........
  • Page 14 12.6.3 SNOOZE mode function....................... 658 12.6.4 Calculating baud rate ........................663 12.6.5 Procedure for processing errors that occurred during UART (UART0 to UART3) communication667 12.7 LIN Communication Operation ....................668 12.7.1 LIN transmission........................... 668 12.7.2 LIN reception ..........................671 12.8 Operation of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) Communication ........................
  • Page 15 13.6 Timing Charts ........................... 769 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR ......... 784 14.1 Functions of Multiplier and Divider/Multiply-Accumulator ..........784 14.2 Configuration of Multiplier and Divider/Multiply-Accumulator .......... 784 14.3 Register Controlling Multiplier and Divider/Multiply-Accumulator........790 14.4 Operations of Multiplier and Divider/Multiply-Accumulator ..........792 14.4.1 Multiplication (unsigned) operation ....................
  • Page 16 CHAPTER 17 KEY INTERRUPT FUNCTION ..................850 17.1 Functions of Key Interrupt ...................... 850 17.2 Configuration of Key Interrupt ....................850 17.3 Register Controlling Key Interrupt ..................852 CHAPTER 18 STANDBY FUNCTION ....................853 18.1 Standby Function and Configuration ..................853 18.1.1 Standby function...........................
  • Page 17 22.3.3 RAM parity error detection function ....................909 22.3.4 RAM guard function........................910 22.3.5 SFR guard function ........................911 22.3.6 Invalid memory access detection function ..................912 22.3.7 Frequency detection function ....................... 914 22.3.8 A/D test function ........................... 916 CHAPTER 23 REGULATOR ......................... 920 23.1 Regulator Overview........................
  • Page 18 25.7.1 Boot swap function ........................949 25.7.2 Flash shield window function......................951 CHAPTER 26 ON-CHIP DEBUG FUNCTION ..................952 26.1 Connecting E1 On-chip Debugging Emulator to RL78/G13 ..........952 26.2 On-Chip Debug Security ID ..................... 953 26.3 Securing of User Resources ....................953 CHAPTER 27 BCD CORRECTION CIRCUIT ..................
  • Page 19 29.6 Peripheral Functions Characteristics................... 1008 29.6.1 Serial array unit .......................... 1008 29.6.2 Serial interface IICA ........................1031 29.6.3 On-chip debug (UART)....................... 1032 29.7 Analog Characteristics ......................1032 29.7.1 A/D converter characteristics...................... 1032 29.7.2 Temperature sensor characteristics ................... 1036 29.7.3 POR circuit characteristics ......................1036 29.7.4 LVD circuit characteristics ......................

  • Page 20: Chapter 1 Outline

    R01UH0146EJ0100 RL78/G13 Rev.1.00 RENESAS MCU Sep 22, 2011 CHAPTER 1 OUTLINE 1.1 Features μ Minimum instruction execution time can be changed from high speed (0.03125 s: @ 32 MHz operation with high- μ speed on-chip oscillator) to ultra low-speed (30.5 s: @ 32.768 kHz operation with subsystem clock)
  • Page 21 RL78/G13 CHAPTER 1 OUTLINE ROM, RAM capacities Flash Data RL78/G13 flash 20 pins 24 pins 25 pins 30 pins 32 pins 36 pins − − − 8 KB R5F100AG R5F100BG R5F100CG − − − − R5F101AG R5F101BG R5F101CG − −...

  • Page 22: Ordering Information

    RL78/G13 CHAPTER 1 OUTLINE 1.2 Ordering Information • Flash memory version (lead-free product) (1/3) Pin count Package Data flash Part Number 20 pins 20-pin plastic SSOP (7.62 mm Mounted R5F1006AASP, R5F1006CASP, R5F1006DASP, R5F1006EASP (300)) Not mounted R5F1016AASP, R5F1016CASP, R5F1016DASP, R5F1016EASP...
  • Page 23 RL78/G13 CHAPTER 1 OUTLINE (2/3) Pin count Package Data flash Part Number 48 pins 48-pin plastic LQFP Mounted R5F100GAAFB, R5F100GCAFB, R5F100GDAFB, (fine pitch) (7 × 7) R5F100GEAFB, R5F100GFAFB, R5F100GGAFB, R5F100GHAFB, R5F100GJAFB, R5F100GKAFB, R5F100GLAFB Not mounted R5F101GAAFB, R5F101GCAFB, R5F101GDAFB, R5F101GEAFB, R5F101GFAFB, R5F101GGAFB, R5F101GHAFB, R5F101GJAFB, R5F101GKAFB, R5F101GLAFB 48-pin plastic WQFN (7 ×...
  • Page 24 RL78/G13 CHAPTER 1 OUTLINE (3/3) Pin count Package Data flash Part Number 80-pin plastic LQFP (14 × 14) 80 pins Mounted R5F100MFAFA, R5F100MGAFA, R5F100MHAFA, R5F100MJAFA, R5F100MKAFA, R5F100MLAFA Not mounted R5F101MFAFA, R5F101MGAFA, R5F101MHAFA, R5F101MJAFA, R5F101MKAFA, R5F101MLAFA 80-pin plastic LQFP (fine pitch)

  • Page 25: Pin Configuration (Top View)

    RL78/G13 CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 20-pin products • 20-pin plastic SSOP (7.62 mm (300)) P01/ANI16/TO00/RxD1 P20/ANI0/AV REFP P00/ANI17/TI00/TxD1 P21/ANI1/AV REFM P40/TOOL0 P22/ANI2 RESET P147/ANI18 P137/INTP0 P10/SCK00/SCL00 P122/X2/EXCLK P11/SI00/RxD0/TOOLRxD/SDA00 P121/X1 P12/SO00/TxD0/TOOLTxD REGC P16/TI01/TO01/INTP5/SO11 P17/TI02/TO02/SI11/SDA11 P30/INTP3/SCK11/SCL11 μ...

  • Page 26: 24-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.3.2 24-pin products • 24-pin plastic WQFN (fine pitch) (4 × 4) exposed die pad 18 17 16 15 14 13 P17/TI02/TO02/SO11 P21/ANI1/AV REFM P50/INTP1/SI11/SDA11 P20/ANI0/AV REFP P30/INTP3/SCK11/SCL11 P01/ANI16/TO00/RxD1 P31/TI03/TO03/INTP4/PCLBUZ0 P00/ANI17/TI00/TxD1 P61/SDAA0 P40/TOOL0 P60/SCLA0 RESET 1 2 3 4 5 6 μ...

  • Page 27: 25-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.3.3 25-pin products • 25-pin plastic FLGA (3 × 3) Bottom View Top View INDEX MARK INDEX MARK P40/TOOL0 RESET P01/ANI16/ P22/ANI2 P147/ANI18 TO00/RxD1 P122/X2/ P137/INTP0 P00/ANI17/ P21/ANI1/ P10/SCK00/ EXCLK TI00/TxD1 SCL00 REFM P121/X1 P20/ANI0/ P12/SO00/...

  • Page 28: 30-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.3.4 30-pin products • 30-pin plastic SSOP (7.62 mm (300)) <R> P20/ANI0/AV P21/ANI1/AV REFP REFM P01/ANI16/TO00/RxD1 P22/ANI2 P00/ANI17/TI00/TxD1 P23/ANI3 P120/ANI19 P147/ANI18 P40/TOOL0 P10/SCK00/SCL00/(TI07)/(TO07) RESET P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P137/INTP0 P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P122/X2/EXCLK P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P121/X1 P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) REGC P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P60/SCLA0...

  • Page 29: 32-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.3.5 32-pin products • 32-pin plastic WQFN (fine pitch) (5 × 5) <R> exposed die pad 24 23 22 21 20 19 18 17 P147/ANI18 P51/INTP2/SO11 P23/ANI3 P50/INTP1/SI11/SDA11 P22/ANI2 P30/INTP3/SCK11/SCL11 P21/ANI1/AV REFM P20/ANI0/AV P31/TI03/TO03/INTP4/PCLBUZ0 REFP P01/ANI16/TO00/RxD1...

  • Page 30: 36-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.3.6 36-pin products <R> • 36-pin plastic FLGA (4 × 4) Top View Bottom View INDEX MARK P60/SCLA0 P121/X1 P122/X2/EXCLK P137/INTP0 P40/TOOL0 P61/SDAA0 REGC RESET P120/ANI19 P72/SO21 P71/SI21/ P14/RxD2/SI20/ P31/TI03/TO03/ P00/TI00/TxD1 P01/TO00/RxD1 SDA21 SDA20/(SCLA0) INTP4/ /(TI03)/(TO03)

  • Page 31: 40-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.3.7 40-pin products <R> • 40-pin plastic WQFN (fine pitch) (6 × 6) 30 29 28 27 26 25 24 23 22 21 P26/ANI6 P50/INTP1/SI11/SDA11 P25/ANI5 exposed die pad P30/INTP3/RTC1HZ/SCK11/SCL11 P24/ANI4 P70/KR0/SCK21/SCL21 P23/ANI3 P71/KR1/SI21/SDA21 P22/ANI2 P72/KR2/SO21...

  • Page 32: 44-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.3.8 44-pin products • 44-pin plastic LQFP (10 × 10) <R> 33 32 31 30 29 28 27 26 25 24 23 P50/INTP1/SI11/SDA11 P27/ANI7 P30/INTP3/RTC1HZ/SCK11/SCL11 P26/ANI6 P70/KR0/SCK21/SCL21 P25/ANI5 P71/KR1/SI21/SDA21 P24/ANI4 P72/KR2/SO21 P23/ANI3 P73/KR3 P22/ANI2 P31/TI03/TO03/INTP4/PCLBUZ0 P21/ANI1/AV...

  • Page 33: 48-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.3.9 48-pin products <R> • 48-pin plastic LQFP (fine pitch) (7 × 7) 36 35 34 33 32 31 30 29 28 27 26 25 P120/ANI19 P147/ANI18 P41/TI07/TO07 P146 P40/TOOL0 P10/SCK00/SCL00/(TI07)/(TO07) RESET P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P124/XT2/EXCLKS P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P123/XT1...
  • Page 34 RL78/G13 CHAPTER 1 OUTLINE • 48-pin plastic WQFN (7 × 7) <R> 36 35 34 33 32 31 30 29 28 27 26 25 P147/ANI18 P120/ANI19 P146 P41/TI07/TO07 exposed die pad P10/SCK00/SCL00/(TI07)/(TO07) P40/TOOL0 P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) RESET P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P124/XT2/EXCLKS P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P123/XT1 P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)

  • Page 35: 52-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.3.10 52-pin products <R> • 52-pin plastic LQFP (10 × 10) 39 38 37 36 35 34 33 32 31 30 29 28 27 P70/KR0/SCK21/SCL21 P27/ANI7 P71/KR1/SI21/SDA21 P26/ANI6 P72/KR2/SO21 P25/ANI5 P73/KR3/SO01 P24/ANI4 P74/KR4/INTP8/SI01/SDA01 P23/ANI3 P75/KR5/INTP9/SCK01/SCL01 P22/ANI2...

  • Page 36: 64-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.3.11 64-pin products • 64-pin plastic LQFP (12 × 12) <R> • 64-pin plastic LQFP (fine pitch) (10 × 10) • 64-pin plastic TQFP (fine pitch) (7 × 7) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33...
  • Page 37 RL78/G13 CHAPTER 1 OUTLINE • 64-pin plastic FBGA (4 × 4) <R> Top View Bottom View C D E H G F E D C B A Index mark Pin No. Name Pin No. Name Pin No. Name Pin No.

  • Page 38: 80-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.3.12 80-pin products • 80-pin plastic LQFP (14 × 14) <R> • 80-pin plastic LQFP (fine pitch) (12 × 12) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41...

  • Page 39: 100-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.3.13 100-pin products • 100-pin plastic LQFP (fine pitch) (14 × 14) <R> 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51...
  • Page 40 RL78/G13 CHAPTER 1 OUTLINE • 100-pin plastic LQFP (14 × 20) <R> 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51...

  • Page 41: 128-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.3.14 128-pin products • 128-pin plastic LQFP (fine pitch) (14 × 20) <R> 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65...

  • Page 42: Pin Identification

    RL78/G13 CHAPTER 1 OUTLINE 1.4 Pin Identification ANI0 to ANI14, PCLBUZ0, PCLBUZ1: Programmable clock output/buzzer ANI16 to ANI26: Analog input output A/D converter reference REGC: Regulator capacitance REFM potential (− side) input RESET: Reset A/D converter reference RTC1HZ: Real-time clock correction clock...

  • Page 43: Block Diagram

    RL78/G13 CHAPTER 1 OUTLINE 1.5 Block Diagram 1.5.1 20-pin products TIMER ARRAY PORT 0 P00, P01 UNIT (8ch) TI00/P00 PORT 1 P10 to P12, P16, P17 TO00/P01 TI01/TO01/P16 PORT 2 P20 to P22 TI02/TO02/P17 PORT 3 PORT 4 P121, P122...

  • Page 44: 24-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.5.2 24-pin products TIMER ARRAY PORT 0 P00, P01 UNIT (8ch) TI00/P00 PORT 1 P10 to P12, P16, P17 TO00/P01 TI01/TO01/P16 PORT 2 P20 to P22 TI02/TO02/P17 PORT 3 P30, P31 TI03/TO03/P31 PORT 4 PORT 5...

  • Page 45: 25-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.5.3 25-pin products TIMER ARRAY PORT 0 P00, P01 UNIT (8ch) TI00/P00 PORT 1 P10 to P12, P16, P17 TO00/P01 TI01/TO01/P16 PORT 2 P20 to P22 TI02/TO02/P17 PORT 3 P30, P31 TI03/TO03/P31 PORT 4 PORT 5...

  • Page 46: 30-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.5.4 30-pin products <R> TIMER ARRAY PORT 0 P00, P01 UNIT (8ch) TI00/P00 PORT 1 P10 to P17 TO00/P01 TI01/TO01/P16 PORT 2 P20 to P23 TI02/TO02/P17 (TI02/TO02/P15) PORT 3 P30, P31 TI03/TO03/P31 (TI03/TO03/P14) PORT 4 (TI04/TO04/P13)

  • Page 47: 32-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.5.5 32-pin products <R> TIMER ARRAY PORT 0 P00, P01 UNIT (8ch) TI00/P00 PORT 1 P10 to P17 TO00/P01 TI01/TO01/P16 PORT 2 P20 to P23 TI02/TO02/P17 (TI02/TO02/P15) PORT 3 P30, P31 TI03/TO03/P31(TI03/TO03/P14) PORT 4 (TI04/TO04/P13) PORT 5...

  • Page 48: 36-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.5.6 36-pin products <R> TIMER ARRAY PORT 0 P00, P01 UNIT (8ch) TI00/P00 PORT 1 P10 to P17 TO00/P01 TI01/TO01/P16 PORT 2 P20 to P25 TI02/TO02/P17 (TI02/TO02/P15) PORT 3 P30, P31 TI03/TO03/P31 (TI03/TO03/P14) PORT 4 (TI04/TO04/P13)

  • Page 49: 40-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.5.7 40-pin products <R> TIMER ARRAY PORT 0 P00, P01 UNIT (8ch) TI00/P00 PORT 1 P10 to P17 TO00/P01 TI01/TO01/P16 PORT 2 P20 to P26 TI02/TO02/P17 (TI02/TO02/P15) PORT 3 P30, P31 TI03/TO03/P31 (TI03/TO03/P14) PORT 4 (TI04/TO04/P13)

  • Page 50: 44-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.5.8 44-pin products <R> TIMER ARRAY PORT 0 P00, P01 UNIT (8ch) TI00/P00 PORT 1 P10 to P17 TO00/P01 TI01/TO01/P16 PORT 2 P20 to P27 TI02/TO02/P17 (TI02/TO02/P15) PORT 3 P30, P31 TI03/TO03/P31 (TI03/TO03/P14) PORT 4 P40, P41...

  • Page 51: 48-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.5.9 48-pin products <R> TIMER ARRAY PORT 0 P00, P01 UNIT (8ch) TI00/P00 PORT 1 P10 to P17 TO00/P01 TI01/TO01/P16 PORT 2 P20 to P27 TI02/TO02/P17 (TI02/TO02/P15) PORT 3 P30, P31 TI03/TO03/P31 (TI03/TO03/P14) PORT 4 P40, P41...

  • Page 52: 52-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.5.10 52-pin products <R> TIMER ARRAY PORT 0 P00 to P03 UNIT (8ch) TI00/P00 PORT 1 P10 to P17 TO00/P01 TI01/TO01/P16 PORT 2 P20 to P27 TI02/TO02/P17 (TI02/TO02/P15) PORT 3 P30, P31 TI03/TO03/P31 (TI03/TO03/P14) PORT 4...

  • Page 53: 64-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.5.11 64-pin products <R> TIMER ARRAY PORT 0 P00 to P06 UNIT (8ch) TI00/P00 PORT 1 P10 to P17 TO00/P01 TI01/TO01/P16 PORT 2 P20 to P27 TI02/TO02/P17 (TI02/TO02/P15) PORT 3 P30, P31 TI03/TO03/P31 (TI03/TO03/P14) PORT 4...

  • Page 54: 80-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE <R> 1.5.12 80-pin products TIMER ARRAY TIMER ARRAY UNIT1 (4ch) UNIT0 (8ch) TI00/P00 PORT 0 P00 to P06 TI10/TO10/P64 TO00/P01 TI11/TO11/P65 PORT 1 TI01/TO01/P16 P10 to P17 TI02/TO02/P17 TI12/TO12/P66 PORT 2 P20 to P27 (TI02/TO02/P15) TI03/TO03/P31...

  • Page 55: 100-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.5.13 100-pin products <R> TIMER ARRAY TIMER ARRAY UNIT1 (4ch) UNIT0 (8ch) TI00/P00 PORT 0 P00 to P06 TI10/TO10/P64 TO00/P01 TI11/TO11/P65 PORT 1 P10 to P17 TI01/TO01/P16 TI02/TO02/P17 TI12/TO12/P66 PORT 2 P20 to P27 (TI02/TO02/P15) TI03/TO03/P31...

  • Page 56: 128-Pin Products

    RL78/G13 CHAPTER 1 OUTLINE 1.5.14 128-pin products <R> TIMER ARRAY TIMER ARRAY UNIT1 (8ch) UNIT0 (8ch) TI00/P00 PORT 0 P00 to P07 TI10/TO10/P64 TO00/P01 TI11/TO11/P65 PORT 1 P10 to P17 TI01/TO01/P16 TI02/TO02/P17 TI12/TO12/P66 PORT 2 P20 to P27 (TI02/TO02/P15) TI03/TO03/P31...

  • Page 57: Outline Of Functions

    RL78/G13 CHAPTER 1 OUTLINE 1.6 Outline of Functions [20-pin, 24-pin, 25-pin, 30-pin, 32-pin, 36-pin products] Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 20-pin 24-pin 25-pin 30-pin...
  • Page 58 RL78/G13 CHAPTER 1 OUTLINE (2/2) Item 20-pin 24-pin 25-pin 30-pin 32-pin 36-pin − Clock output/buzzer output • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: f = 20 MHz operation) MAIN •...
  • Page 59 RL78/G13 CHAPTER 1 OUTLINE [40-pin, 44-pin, 48-pin, 52-pin, 64-pin products] Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 40-pin 44-pin 48-pin 52-pin 64-pin Code flash memory (KB)
  • Page 60 RL78/G13 CHAPTER 1 OUTLINE (2/2) Item 40-pin 44-pin 48-pin 52-pin 64-pin Clock output/buzzer output • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: f = 20 MHz operation) MAIN • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: f = 32.768 kHz operation)
  • Page 61 RL78/G13 CHAPTER 1 OUTLINE [80-pin, 100-pin, 128-pin products] (1/2) Item 80-pin 100-pin 128-pin R5F100Mx R5F101Mx R5F100Px R5F101Px R5F100Sx R5F101Sx Code flash memory (KB) 96 to 512 96 to 512 192 to 512 − − − Data flash memory (KB) Note1...
  • Page 62 RL78/G13 CHAPTER 1 OUTLINE (2/2) Item 80-pin 100-pin 128-pin R5F100Mx R5F101Mx R5F100Px R5F101Px R5F100Sx R5F101Sx Clock output/buzzer output • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: f = 20 MHz operation) MAIN •...

  • Page 63: Chapter 2 Pin Functions

    RL78/G13 CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies...

  • Page 64: 20-Pin Products

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.1 20-pin products Function Name Function After Reset Alternate Function Port 0. Analog input ANI17/TI00/TxD1 2-bit I/O port. port ANI16/TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (V tolerance).

  • Page 65: 24-Pin Products

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.2 24-pin products Function Name Function After Reset Alternate Function Port 0. Analog input ANI17/TI00/TxD1 2-bit I/O port. port ANI16/TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (V tolerance).

  • Page 66: 25-Pin Products

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.3 25-pin products Function Name Function After Reset Alternate Function Port 0. Analog input ANI17/TI00/TxD1 2-bit I/O port. port ANI16/TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (V tolerance).

  • Page 67: 30-Pin Products

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.4 30-pin products <R> (1/2) Function Name Function After Reset Alternate Function Port 0. Analog input ANI17/TI00/TxD1 2-bit I/O port. port ANI16/TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (V tolerance).
  • Page 68 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name Function After Reset Alternate Function Port 5. Input port INTP1/SI11/SDA11 2-bit I/O port. INTP2/SO11 Output of P50 can be set to N-ch open-drain output (V tolerance). Input/output can be specified in 1-bit units.

  • Page 69: 32-Pin Products

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.5 32-pin products <R> (1/2) Function Name Function After Reset Alternate Function Port 0. Analog input ANI17/TI00/TxD1 2-bit I/O port. port ANI16/TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (V tolerance).
  • Page 70 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name Function After Reset Alternate Function Port 5. Input port INTP1/SI11/SDA11 2-bit I/O port. INTP2/SO11 Output of P50 can be set to N-ch open-drain output (V tolerance). Input/output can be specified in 1-bit units.

  • Page 71: 36-Pin Products

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.6 36-pin products <R> (1/2) Function Name Function After Reset Alternate Function Port 0. Input port TI00/TxD1 2-bit I/O port. TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (V tolerance).
  • Page 72 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name Function After Reset Alternate Function Port 5. Input port INTP1/SI11/SDA11 2-bit I/O port. INTP2/SO11 Output of P50 can be set to N-ch open-drain output (V tolerance). Input/output can be specified in 1-bit units.

  • Page 73: 40-Pin Products

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.7 40-pin products <R> (1/2) Function Name Function After Reset Alternate Function Port 0. Input port TI00/TxD1 2-bit I/O port. TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (V tolerance).
  • Page 74 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name Function After Reset Alternate Function Port 5. Input port INTP1/SI11/SDA11 2-bit I/O port. INTP2/SO11 Output of P50 can be set to N-ch open-drain output (V tolerance). Input/output can be specified in 1-bit units.

  • Page 75: 44-Pin Products

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.8 44-pin products <R> (1/2) Function Name Function After Reset Alternate Function Port 0. Input port TI00/TxD1 2-bit I/O port. TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (V tolerance).
  • Page 76 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name Function After Reset Alternate Function Port 5. Input port INTP1/SI11/SDA11 2-bit I/O port. INTP2/SO11 Output of P50 can be set to N-ch open-drain output (V tolerance). Input/output can be specified in 1-bit units.

  • Page 77: 48-Pin Products

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.9 48-pin products <R> (1/2) Function Name Function After Reset Alternate Function Port 0. Input port TI00/TxD1 2-bit I/O port. TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (V tolerance).
  • Page 78 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name Function After Reset Alternate Function Port 5. Input port INTP1/SI11/SDA11 2-bit I/O port. INTP2/SO11 Output of P50 can be set to N-ch open-drain output (V tolerance). Input/output can be specified in 1-bit units.

  • Page 79: 52-Pin Products

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.10 52-pin products <R> (1/2) Function Name Function After Reset Alternate Function Port 0. Input port TI00 4-bit I/O port. TO00 Input of P01 and P03 can be set to TTL input buffer. Analog input...
  • Page 80 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name Function After Reset Alternate Function Port 5. Input port INTP1/SI11/SDA11 2-bit I/O port. INTP2/SO11 Output of P50 can be set to N-ch open-drain output (V tolerance). Input/output can be specified in 1-bit units.

  • Page 81: 64-Pin Products

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.11 64-pin products <R> (1/2) Function Name Function After Reset Alternate Function Port 0. Input port TI00 7-bit I/O port. TO00 Input of P01, P03, and P04 can be set to TTL input buffer. Analog input...
  • Page 82 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name Function After Reset Alternate Function Port 5. Input port INTP1/SI11/SDA11 6-bit I/O port. INTP2/SO11 Output of P50 can be set to N-ch open-drain output (V (INTP10) tolerance). (INTP11) Input/output can be specified in 1-bit units.

  • Page 83: 80-Pin Products

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.12 80-pin products <R> (1/3) Function Name Function After Reset Alternate Function Port 0. Input port TI00 7-bit I/O port. TO00 Input of P01, P03 and P04 can be set to TTL input buffer. Analog input...
  • Page 84 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/3) Function Name Function After Reset Alternate Function Port 4. Input port TOOL0 6-bit I/O port. TI07/TO07 Input of P43 and P44 can be set to TTL input buffer. TI04/TO04 Output of P43 to P45 can be set to N-ch open-drain output SCK01/SCL01 tolerance).
  • Page 85 RL78/G13 CHAPTER 2 PIN FUNCTIONS (3/3) Function Name Function After Reset Alternate Function − P130 Output Port 13. Output port 1-bit output port and 1-bit input port. P137 Input Input port INTP0 P140 Port 14. Input port PCLBUZ0/INTP6 7-bit I/O port.

  • Page 86: 100-Pin Products

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.13 100-pin products <R> (1/3) Function Name Function After Reset Alternate Function Port 0. Input port TI00 7-bit I/O port. TO00 Input of P01, P03 and P04 can be set to TTL input buffer. Analog input...
  • Page 87 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/3) Function Name Function After Reset Alternate Function Port 4. Input port TOOL0 8-bit I/O port. − Input of P43 and P44 can be set to TTL input buffer. TI04/TO04 Output of P43 to P45 can be set to N-ch open-drain output SCK01/SCL01 tolerance).
  • Page 88 RL78/G13 CHAPTER 2 PIN FUNCTIONS (3/3) Function Name Function After Reset Alternate Function P100 Port 10. Analog input ANI20 3-bit I/O port. port − P100 can be set to analog input. P101 Input port P102 TI06/TO06 P110 Port 11. Input port (INTP10) 2-bit I/O port.

  • Page 89: 128-Pin Products

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.14 128-pin products <R> (1/4) Function Name Function After Reset Alternate Function Port 0. Input port TI00 8-bit I/O port. TO00 Input of P01, P03 and P04 can be set to TTL input buffer. Analog input...
  • Page 90 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/4) Function Name Function After Reset Alternate Function Port 3. Input port INTP3/RTC1HZ 8-bit I/O port. TI03/TO03/INTP4/ P35 to P37 can be set to analog input. (PCLBUZ0) Input/output can be specified in 1-bit units. −...
  • Page 91 RL78/G13 CHAPTER 2 PIN FUNCTIONS (3/4) Function Name Function After Reset Alternate Function Port 7. Input port KR0/SCK21/SCL21 8-bit I/O port. KR1/SI21/SDA21 Output of P71 and P74 can be set to N-ch open-drain output KR2/SO21 tolerance). Input/output can be specified in 1-bit units.
  • Page 92 RL78/G13 CHAPTER 2 PIN FUNCTIONS (4/4) Function Name Function After Reset Alternate Function P120 Port 12. Analog input ANI19 4-bit I/O port and 4-bit input port. port P120 can be set to analog input. P121 Input Input port For only P120, P125 to P127, input/output can be specified in...

  • Page 93: Pins For Each Product (Pins Other Than Port Pins)

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.15 Pins for each product (pins other than port pins) (1/6) Function Function 128- Name -pin √ √ √ √ √ √ √ √ √ √ √ √ √ √ A/D converter analog ANI0 Input input √...
  • Page 94 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/6) Function Function 128- Name -pin √ √ √ √ √ √ √ √ − − − − − − Input Key interrupt input √ √ √ √ √ √ √ √ − − −...
  • Page 95 RL78/G13 CHAPTER 2 PIN FUNCTIONS (3/6) Function Function 128- Name -pin √ √ √ √ √ √ √ √ √ √ √ √ √ √ SCL00 Output Clock output for IIC00, IIC01, IIC10, IIC11, IIC20, √ √ √ √ √...
  • Page 96 RL78/G13 CHAPTER 2 PIN FUNCTIONS (4/6) Function Function 128- Name -pin √ √ √ √ √ √ √ √ √ √ √ √ √ √ TI00 Input External count clock input to 16-bit timer 00 √ √ √ √ √...
  • Page 97 RL78/G13 CHAPTER 2 PIN FUNCTIONS (5/6) Function Function 128- Name -pin √ √ √ − − − − − − − − − − − TO10 16-bit timer 10 output Output √ √ √ − − − − − −...
  • Page 98 RL78/G13 CHAPTER 2 PIN FUNCTIONS (6/6) Function Function 128- Name -pin − √ √ √ √ √ √ √ √ √ √ √ √ √ √ <20-pin, 24-pin, 25-pin, 30- pin, 32-pin, 36-pin, 40-pin, 44-pin, 48-pin, 52-pin> Positive power supply for all pins <64-pin, 80-pin, 100-pin,...

  • Page 99: Description Of Pin Functions

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions Remark The pins mounted depend on the product. See 1.3 Pin Configuration (Top View) and 2.1 Pin Function List. 2.2.1 P00 to P07 (port 0) P00 to P07 function as an I/O port. These pins also function as timer I/O, A/D converter analog input, serial interface data I/O, and clock I/O.

  • Page 100: P10 To P17 (Port 1)

    RL78/G13 CHAPTER 2 PIN FUNCTIONS (h) SCL10 This is a serial clock output pin of serial interface IIC10. TI00, TI05, TI06 There are the pins for inputting an external count clock/capture trigger to 16-bit timers 00, 05, and 06. TO00, TO05, TO06 These are the timer output pins of 16-bit timers 00, 05, and 06.

  • Page 101: P20 To P27 (Port 2)

    RL78/G13 CHAPTER 2 PIN FUNCTIONS (h) TO01, TO02 These are the timer output pins of 16-bit timers 01 and 02. TOOLTxD This UART serial data output pin for an external device connection is used during flash memory programming. TOOLRxD This UART serial data input pin for an external device connection is used during flash memory programming.

  • Page 102: P40 To P47 (Port 4)

    RL78/G13 CHAPTER 2 PIN FUNCTIONS (1) Port mode P30 to P37 function as an I/O port. P30 and P31 can be set to input or output port in 1-bit units using port mode register 3 (PM3). (2) Control mode P30 to P37 function as A/D converter analog input, external interrupt request input, real-time clock correction clock output, serial interface data I/O, clock I/O, clock/buzzer output, and timer I/O.
  • Page 103 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2) Control mode P40 to P47 function as serial interface data I/O, clock I/O, external interrupt request input, data I/O for a flash memory programmer/debugger, and timer I/O. (a) TI04, TI05, TI07 These are the pins for inputting an external count clock/capture trigger to 16-bit timers 04, 05, and 07.

  • Page 104: P50 To P57 (Port 5)

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.2.6 P50 to P57 (port 5) P50 to P57 function as an I/O port. These pins also function as external interrupt request input, serial interface data I/O, and clock I/O. Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5).

  • Page 105: P70 To P77 (Port 7)

    RL78/G13 CHAPTER 2 PIN FUNCTIONS (a) SCLA0, SCLA1 These are the serial clock I/O pins of serial interface IICA. (b) SDAA0, SDAA1 These are the serial data I/O pins of serial interface IICA. (c) TI10, TI11, TI12, TI13 These are the pins for inputting an external count clock/capture trigger to 16-bit timers 10, 11, 12, and 13.

  • Page 106: P80 To P87 (Port 8)

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.2.9 P80 to P87 (port 8) P80 to P87 function as an I/O port. Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 8 (PU8). Input to the P80 and P81 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units, using port input mode register 8 (PIM8).

  • Page 107: P110 To P117 (Port 11)

    RL78/G13 CHAPTER 2 PIN FUNCTIONS (1) Port mode P100 to P106 function as an I/O port. P100 to P106 can be set to input or output port in 1-bit units using port mode register 10 (PM10). (2) Control mode P100 to P106 function as serial interface data I/O and clock I/O. These pins also function as A/D converter analog input and timer I/O.

  • Page 108: P130, P137 (Port 13)

    RL78/G13 CHAPTER 2 PIN FUNCTIONS (1) Port mode P120 and P125 to P127 function as a 1-bit I/O port. P120 can be set to input or output port using port mode register 12 (PM12). P121 to P124 functions as a 4-bit input port.
  • Page 109 RL78/G13 CHAPTER 2 PIN FUNCTIONS <R> When the P147 pin is used as input, specify them as either digital or analog in Port mode control register 14 (PMC14). This register can be specified in 1-bit unit. The following operation modes can be specified in 1-bit units.

  • Page 110: P150 To P156 (Port 15)

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.2.16 P150 to P156 (port 15) P150 to P156 function as an I/O port. These pins also function as A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode P150 to P156 function as an I/O port.

  • Page 111: Pin I/O Circuits And Recommended Connection Of Unused Pins

    RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-3 shows the types of pin I/O circuits and the recommended connections of unused pins. <R> Table 2-3. Connection of Unused Pins (128-pin products) (1/4)
  • Page 112 RL78/G13 CHAPTER 2 PIN FUNCTIONS <R> Table 2-3. Connection of Unused Pins (128-pin products) (2/4) Pin Name I/O Circuit Type Recommended Connection of Unused Pins P30/INTP3/RTC1HZ Input: Independently connect to EV , EV or EV , EV via a resistor.
  • Page 113 RL78/G13 CHAPTER 2 PIN FUNCTIONS <R> Table 2-3. Connection of Unused Pins (128-pin products) (3/4) Pin Name I/O Circuit Type Recommended Connection of Unused Pins P70/KR0/SCK21/SCL21 Input: Independently connect to EV , EV or EV , EV via a resistor.
  • Page 114 RL78/G13 CHAPTER 2 PIN FUNCTIONS Table 2-3. Connection of Unused Pins (128-pin products) (4/4) <R> Pin Name I/O Circuit Type Recommended Connection of Unused Pins P115/ANI26 11-U Input: Independently connect to EV , EV or EV , EV via a resistor.
  • Page 115 RL78/G13 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) <R> Type 2 Type 3-C P-ch data N-ch Schmitt-triggered input with hysteresis characteristics Type 5-AN Type 8-R pull-up P-ch enable pullup P-ch enable data P-ch IN/OUT output N-ch...
  • Page 116 RL78/G13 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) <R> Type 11-G Type 11-T data P-ch IN/OU data P-ch output N-ch disable IN/OU output N-ch disable P-ch Comparator N-ch Comparator P-ch Series resistor string voltage N-ch Series resistor string voltage...

  • Page 117: Chapter 3 Cpu Architecture

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the RL78/G13 can access a 1 MB memory space. Figures 3-1 to 3-10 show the memory maps. R01UH0146EJ0100 Rev.1.00 Sep 22, 2011...
  • Page 118 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (R5F100xA, R5F101xA(x = 6 to 8, A to C, E to G)) <R> F F F F F H 0 3 F F F H Special function register (SFR) 256 bytes...
  • Page 119 RL78/G13 CHAPTER 3 CPU ARCHITECTURE <R> Figure 3-2. Memory Map (R5F100xC, R5F101xC(x = 6 to 8, A to C, E to G, J, L)) F F F F F H 0 7 F F F H Special function register (SFR)
  • Page 120 RL78/G13 CHAPTER 3 CPU ARCHITECTURE <R> Figure 3-3. Memory Map (R5F100xD, R5F101xD(x = 6 to 8, A to C, E to G, J, L)) F F F F F H 0 B F F F H Special function register (SFR)
  • Page 121 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map (R5F100xE, R5F101xE(x = 6 to 8, A to C, E to G, J, L)) 0 F F F F H F F F F F H Special function register (SFR) 256 bytes...
  • Page 122 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map (R5F100xF, R5F101xF(x = A to C, E to G, J, L, M, P)) 1 7 F F F H F F F F F H Special function register (SFR) 256 bytes...
  • Page 123 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Memory Map (R5F100xG, R5F101xG(x = A to C, E to G, J, L, M, P)) 1 F F F F H F F F F F H Special function register (SFR) 256 bytes...
  • Page 124 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Memory Map (R5F100xH, R5F101xH(x = E to G, J, L, M, P, S)) F F F F F H 2 F F F F H Special function register (SFR) 256 bytes F F F 0 0 H...
  • Page 125 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Memory Map (R5F100xJ, R5F101xJ(x = F, G, J, L, M, P, S)) 3 F F F F H F F F F F H Special function register (SFR) 256 bytes F F F 0 0 H...
  • Page 126 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Memory Map (R5F100xK, R5F101xK(x = F, G, J, L, M, P, S)) 5 F F F F H F F F F F H Special function register (SFR) 256 bytes F F F 0 0 H...
  • Page 127 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Memory Map (R5F100xL, R5F101xL(x = F, G, J, L, M, P, S)) 7 F F F F H F F F F F H Special function register (SFR) 256 bytes F F F 0 0 H...
  • Page 128 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory. 0 F F F F H...
  • Page 129 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory (1/4) Address Value Block Address Value Block Address Value...
  • Page 130 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory (2/4) Address Value Block Address Value Block Address Value Block Address Value Block Number Number Number Number 20000H to 203FFH 28000H to 283FFH...
  • Page 131 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory (3/4) Address Value Block Address Value Block Address Value Block Address Value Block Number Number Number Number 40000H to 403FFH 100H 48000H to 483FFH...
  • Page 132 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory (4/4) Address Value Block Address Value Block Address Value Block Address Value Block Number Number Number Number 60000H to 603FFH 180H 68000H to 683FFH...

  • Page 133: Internal Program Memory Space

    CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. The RL78/G13 products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM...
  • Page 134 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table (1/2) Vector Table Address Interrupt Source √ √ √ √ √ √ √ √ √ √ √ √ √ √ 0000H RESET, POR, LVD, WDT, TRAP, IAW, RAMTOP √ √ √...
  • Page 135 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table (2/2) Vector Table Address Interrupt Source √ √ √ √ √ √ √ √ √ √ √ √ √ √ 0042H INTTM04 √ √ √ √ √ √ √ √ √...

  • Page 136: Mirror Area

    3.1.2 Mirror area The RL78/G13 mirrors the code flash area of 00000H to 0FFFFH, to F0000H to FFFFFH. The products with 96 KB or more flash memory mirror the code flash area of 00000H to 0FFFFH or 10000H to 1FFFFH, to F0000H to FFFFFH (the code flash area to be mirrored is set by the processor mode control register (PMC)).
  • Page 137 RL78/G13 CHAPTER 3 CPU ARCHITECTURE • Processor mode control register (PMC) This register sets the flash memory space for mirroring to area from F0000H to FFFFFH. The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 138: Internal Data Memory Space

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.1.3 Internal data memory space The RL78/G13 products incorporate the following RAMs. Table 3-4. Internal RAM Capacity Part Number Internal RAM 2048 × 8 bits (FF700H to FFEFFH) R5F100xA, R5F101xA (x = 6 to 8, A to C, E to G) R5F100xC, R5F101xC (x = 6 to 8, A to C, E to G, J, L) 3072 ×...

  • Page 139: Special Function Register (Sfr) Area

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table 3-5 in 3.2.4 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned.

  • Page 140: Data Memory Addressing

    Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the RL78/G13, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of the special function registers (SFR) and general-purpose registers are available for use.
  • Page 141 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Correspondence Between Data Memory and Addressing <R> (R5F100xC, R5F101xC (x = 6 to 8, A to C, E to G, J, L)) F F F F F H SFR addressing Special function register (SFR)
  • Page 142 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-14. Correspondence Between Data Memory and Addressing <R> (R5F100xD, R5F101xD(x = 6 to 8, A to C, E to G, J, L)) F F F F F H SFR addressing Special function register (SFR)
  • Page 143 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-15. Correspondence Between Data Memory and Addressing (R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L)) F F F F F H Special function register (SFR) SFR addressing...
  • Page 144 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-16. Correspondence Between Data Memory and Addressing (R5F100xF, R5F101xF (x = A to C, E to G, J, L, M, P)) F F F F F H Special function register (SFR) SFR addressing F F F 2 0 H...
  • Page 145 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-17. Correspondence Between Data Memory and Addressing (R5F100xG, R5F101xG (x = A to C, E to G, J, L, M, P)) F F F F F H Special function register (SFR) SFR addressing F F F 2 0 H...
  • Page 146 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-18. Correspondence Between Data Memory and Addressing (R5F100xH, R5F101xH (x = E to G, J, L, M, P, S)) F F F F F H Special function register (SFR) SFR addressing F F F 2 0 H...
  • Page 147 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-19. Correspondence Between Data Memory and Addressing (R5F100xJ, R5F101xJ (x = F, G, J, L, M, P, S)) F F F F F H Special function register (SFR) SFR addressing F F F 2 0 H...
  • Page 148 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-20. Correspondence Between Data Memory and Addressing (R5F100xK, R5F101xK (x = F, G, J, L, M, P, S)) F F F F F H Special function register (SFR) SFR addressing F F F 2 0 H...
  • Page 149 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-21. Correspondence Between Data Memory and Addressing (R5F100xL, R5F101xL (x = F, G, J, L, M, P, S)) F F F F F H Special function register (SFR) SFR addressing F F F 2 0 H...

  • Page 150: Processor Registers

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The RL78/G13 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
  • Page 151 RL78/G13 CHAPTER 3 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flags (ISP1, ISP0) This flag manages the priority of acknowledgeable maskable vectored interrupts.

  • Page 152: General-Purpose Registers

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-25. Data to Be Saved to Stack Memory PUSH PSW instruction PUSH rp instruction SP←SP−2 SP←SP−2 ↑ ↑ Register pair lower SP−2 SP−2 ↑ ↑ SP−1 SP−1 Register pair higher ↑ ↑ → →...
  • Page 153 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-26. Configuration of General-Purpose Registers (a) Function name 16-bit processing 8-bit processing FFEFFH Register bank 0 FFEF8H Register bank 1 FFEF0H Register bank 2 FFEE8H Register bank 3 FFEE0H (b) Absolute name 16-bit processing...

  • Page 154: Es And Cs Registers

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.2.3 ES and CS registers The ES register is used for data access and the CS register is used to specify the higher address when a branch instruction is executed. The default value of the ES register after reset is 0FH, and that of the CS register is 00H.

  • Page 155: Special Function Registers (Sfrs)

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
  • Page 156 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (1/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit √ √ − FFF00H Port register 0 √ √ − FFF01H Port register 1 √...
  • Page 157 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (2/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit √ √ − FFF2AH Port mode register 10 PM10 √ √ − FFF2BH Port mode register 11 PM11 √...
  • Page 158 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (3/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit − − √ FFF6AH Timer data register 05 TDR05 0000H FFF6BH − − √ FFF6CH...
  • Page 159 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (4/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit − √ − FFFA0H Clock operation mode control register √ √ − FFFA1H Clock operation status control register √...
  • Page 160 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (5/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit √ √ √ FFFD8H Priority specification flag register PR02L PR02 √ √ FFFD9H Priority specification flag register PR02H √...

  • Page 161: Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2 SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area.
  • Page 162 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2 SFR) List (1/8) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit √ √ − F0010H A/D converter mode register 2 ADM2 − √...
  • Page 163 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (2/8) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit √ √ − F0070H Noise filter enable register 0 NFEN0 √ √...
  • Page 164 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (3/8) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit − − √ F0110H Serial mode register 00 SMR00 0020H F0111H −...
  • Page 165 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (4/8) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit − √ √ F0148H Serial flag clear trigger register SIR10L SIR10 R/W 0000H −...
  • Page 166 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (5/8) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit − − √ F0180H Timer counter register 00 TCR00 FFFFH F0181H −...
  • Page 167 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (6/8) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit − √ √ F01A4H Timer status register 02 TSR02L TSR02 0000H −...
  • Page 168 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (7/8) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit − − √ F01C8H Timer counter register 14 TCR14 FFFFH F01C9H −...
  • Page 169 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (8/8) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit √ √ √ F01F4H Timer channel stop register 1 TT1L 0000H −...

  • Page 170: Instruction Address Addressing

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: −128 to +127 or −32768 to +32767) to the program counter (PC)’s value (the start address of the next instruction), and specifies the program address to be used as the branch destination.

  • Page 171: Table Indirect Addressing

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address.

  • Page 172: Register Direct Addressing

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register direct addressing [Function] Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair (AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and specifies the program address.

  • Page 173: Addressing For Processing Data Addresses

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4 Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word.

  • Page 174: Direct Addressing

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier Description ADDR16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable)

  • Page 175: Short Direct Addressing

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH. [Operand format]...

  • Page 176: Sfr Addressing

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format]...

  • Page 177: Register Indirect Addressing

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description − [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) −...

  • Page 178: Based Addressing

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word as a base address, and 8- bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address.
  • Page 179 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-42. Example of [HL + byte], [DE + byte] FFFFFH rp (HL/DE) Target memory F0000H OP code byte Memory Figure 3-43. Example of word[B], word[C] FFFFFH r (B/C) Target memory F0000H OP code Low Addr.
  • Page 180 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-45. Example of ES:[HL + byte], ES:[DE + byte] FFFFFH rp (HL/DE) Target memory OP code 00000H byte Memory Figure 3-46. Example of ES:word[B], ES:word[C] FFFFFH r (B/C) Target memory OP code 00000H Low Addr.

  • Page 181: Based Indexed Addressing

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address.

  • Page 182: Stack Addressing

    RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request.

  • Page 183: Chapter 4 Port Functions

    • Pins other than port pins The RL78/G13 microcontrollers are provided with digital I/O ports, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS.

  • Page 184: Port Configuration

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-2. Port Configuration (1/2) Item Configuration Control registers Port mode registers (PM0 to PM12, PM14, PM15) Port registers (P0 to P15) Pull-up resistor option registers (PU0, PU1, PU3 to PU12, PU14)
  • Page 185 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Configuration (2/2) Item Configuration • 80-pin products Port Total: 74 (CMOS I/O: 64, CMOS input: 5, CMOS output: 1, N-ch open drain I/O: 4) • 100-pin products Total: 92 (CMOS I/O: 82, CMOS input: 5, CMOS output: 1, N-ch open drain I/O: 4) •...

  • Page 186: Port 0

    RL78/G13 CHAPTER 4 PORT FUNCTIONS Caution Most of the following descriptions in this chapter use the 128-pin products with the 00H setting in peripheral I/O redirection register (PIOR) as an example. 4.2.1 Port 0 Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0).
  • Page 187 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-3. Settings of Registers When Using Port 0 <R> Pin Name PM0× PIM0× POM0× PMC0× Alternate Function Setting Remark Name Note 1 − × × Input Note 1 Note 3 TxD1 output = 1...
  • Page 188 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-1 to 4-6 show block diagrams of port 0 for 128-pin products when PIOR = 00H. <R> Figure 4-1. Block Diagram of P00 PU00 P-ch Alternate function PORT Output latch P00/TI00 (P00)
  • Page 189 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P01 PIM0 PIM01 PU01 P-ch CMOS PORT Output latch P01/TO00 (P01) PM01 Alternate function Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 PIM0: Port input mode register 0 Read signal WR××: Write signal...
  • Page 190 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P02 PU02 P-ch PMC0 PMC02 PORT Output latch (P02) P02/SO10/TxD1/ANI17 POM0 POM02 PM02 Alternate function A/D converter Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0...
  • Page 191 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P03 PIM0 PIM03 PU03 P-ch PMC0 PMC03 Alternate function CMOS PORT Output latch P03/SI10/RxD1/ (P03) SDA10/ANI16 POM0 POM03 PM03 Alternate function A/D converter Port register 0 PU0: Pull-up resistor option register 0...
  • Page 192 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P04 PIM0 PIM04 PU04 P-ch Alternate function CMOS PORT Output latch P04/SCK10/SCL10 (P04) POM0 POM04 PM04 Alternate function Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0...
  • Page 193 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P05 and P07 PU05 to PU07 P-ch PORT Output latch P05 to P07 (P05 to P07) PM05 to PM07 Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal...

  • Page 194: Port 1

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
  • Page 195 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-4. Settings of Registers When Using Port 1 (2/2) <R> Note 10 Pin Name PM1× PIM1× POM1× PMC×× Alternate Function Setting Remark Name × − × Input CMOS input × × TTL input Note 4 ×...
  • Page 196 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> For example, figures 4-7 to 4-14 show block diagrams of port 1 for 128-pin products when PIOR = 00H. Figure 4-7. Block Diagram of P10 PIM1 PIM10 PU10 P-ch Alternate function CMOS PORT Output latch...
  • Page 197 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P11 PIM1 PIM11 PU11 P-ch Alternate function CMOS PORT Output latch P11/SI00/RxD0/ (P11) SDA00/TOOLRxD POM1 POM11 PM11 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1...
  • Page 198 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P12 PU12 P-ch PORT Output latch P12/SO00/ (P12) TxD0/TOOLTxD POM1 POM12 PM12 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 POM1: Port output mode register 1 Read signal WR××: Write signal...
  • Page 199 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P13 <R> PIM1 PIM13 PU13 P-ch CMOS PORT Output latch P13/TxD2/SO20 (P13) POM1 POM13 PM13 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1...
  • Page 200 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P14 PIM1 PIM14 PU14 P-ch Alternate function CMOS PORT Output latch P14/SI20/RxD2/SDA20 (P14) POM1 POM14 PM14 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1...
  • Page 201 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P15 PIM1 PIM15 PU15 P-ch Alternate function CMOS PORT Output latch P15/SCK20/SCL20 (P15) POM1 POM15 PM15 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1...
  • Page 202 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P16 PIM1 PIM16 PU16 P-ch Alternate function CMOS PORT Output latch P16/TI01/TO01/INTP5 (P16) PM16 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1...
  • Page 203 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P17 PIM1 PIM17 PU17 P-ch Alternate function CMOS PORT Output latch P17/TI02/TO02 (P17) POM1 POM17 PM17 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1...

  • Page 204: Port 2

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be used for A/D converter analog input and reference voltage input.
  • Page 205 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figure 4-15 shows a block diagram of port 2 for 128-pin products when PIOR = 00H. <R> Figure 4-15. Block Diagram of P20 to P27 <R> ADPC ADPC 0:Analog input 1:Digital I/O ADPC3 to ADPC0...

  • Page 206: Port 3

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P37 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3).
  • Page 207 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> For example, figures 4-16 to 4-19 show block diagrams of port 3 for 128-pin products when PIOR = 00H. Figure 4-16. Block Diagram of P30 PU30 P-ch Alternate function PORT Output latch P30/RTC1HZ/INTP3 (P30)
  • Page 208 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P31 PU31 P-ch Alternate function PORT Output latch P31/TI03/TO03/INTP4 (P31) PM31 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal R01UH0146EJ0100 Rev.1.00...
  • Page 209 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P32 to P34 PU32 to PU34 P-ch PORT Output latch P32 to P34 (P32 to P34) PM32 to PM34 Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal...
  • Page 210 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P35 to P37 PU35 to PU37 P-ch PMC3 PMC35 to PMC37 PORT Output latch P35/ANI23 to (P35 to P37) P37/ANI21 PM35 to PM37 A/D converter Port register 3 PU3: Pull-up resistor option register 3...

  • Page 211: Port 4

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 to P47 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4).
  • Page 212 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-8. Settings of Registers When Using Port 4 <R> Pin Name PM4× PIM4× POM4× Alternate Function Setting Remark Name − − × Input × Output − − × Input Note 1 TO07 output = 0 Output −...
  • Page 213 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> For example, figures 4-20 to 4-26 show block diagrams of port 4 for 128-pin products when PIOR = 00H. Figure 4-20. Block Diagram of P40 PU40 P-ch Alternate function PORT Output latch (P40) P40/TOOL0...
  • Page 214 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of P41 PU41 P-ch PORT Output latch (P41) PM41 Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal R01UH0146EJ0100 Rev.1.00 Sep 22, 2011...
  • Page 215 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of P42 PU42 P-ch Alternate function PORT Output latch P42/TI04/TO04 (P42) PM42 Alternate function Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal R01UH0146EJ0100 Rev.1.00...
  • Page 216 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of P43, P44 <R> PIM4 PIM43, PIM44 PU43, PU44 P-ch Alternate function CMOS PORT Output latch P43/SCK01/SCL01, (P43. P44) P44/SI01/SDA01 POM4 POM43, POM44 PM43, PM44 Alternate function Port register 4 PU4:...
  • Page 217 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of P45 PU45 P-ch PORT Output latch (P45) P45/SO01 POM4 POM45 PM45 Alternate function Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 POM4: Port output mode register 4 Read signal WR××: Write signal...
  • Page 218 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of P46 <R> PU46 P-ch Alternate function PORT Output latch P46/TI05/TO05/INTP1 (P46) PM46 Alternate function Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal...
  • Page 219 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-26. Block Diagram of P47 <R> PU47 P-ch Alternate function PORT Output latch P47/INTP2 (P47) PM47 Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal R01UH0146EJ0100 Rev.1.00...

  • Page 220: Port 5

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 5 Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (PU5).
  • Page 221 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-9. Settings of Registers When Using Port 5 <R> Note 5 Pin Name PM5× PIM5× POM5× Alternate Function Setting Remark Name − × × Input Note 1 SDA11 output = 1 Output CMOS output N-ch O.D.
  • Page 222 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> For example, figures 4-27 to 4-31 show block diagrams of port 5 for 128-pin products when PIOR = 00H. Figure 4-27. Block Diagram of P50 PU50 P-ch PORT Output latch (P50) POM5 POM50 PM50...
  • Page 223 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-28. Block Diagram of P51, P56, P57 PU51, PU56, PU57 P-ch PORT Output latch P51, P56, P57 (P51, P56, P57) PM51, PM56, PM57 Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 Read signal WR××: Write signal...
  • Page 224 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-29. Block Diagram of P52 PU52 P-ch PORT Output latch P52/SO31 (P52) POM5 POM52 PM52 Alternate function Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 POM5: Port output mode register 5 Read signal WR××: Write signal...
  • Page 225 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-30. Block Diagram of P53, P54 PIM5 PIM53, PIM54 PU53, PU54 P-ch Alternate function CMOS PORT Output latch P53/SI31/SDA31, (P53, P54) P54/SCK31/SCL31 POM5 POM53, POM54 PM53, PM54 Alternate function Port register 5 PU5: Pull-up resistor option register 5...
  • Page 226 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-31. Block Diagram of P55 PIM5 PIM55 PU55 P-ch CMOS PORT Output latch (P55) POM5 POM55 PM55 Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 PIM5: Port input mode register 5...

  • Page 227: Port 6

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 6 Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). When the P64 to P67 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 6 (PU6).
  • Page 228 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> For example, figures 4-32 and 4-33 show block diagrams of port 6 for 128-pin products when PIOR = 00H Figure 4-32. Block Diagram of P60 to P63 Alternate function PORT P60/SCLA0, Output latch P61/SDAA0,...
  • Page 229 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-33. Block Diagram of P64 to P67 PU64 to PU67 P-ch Alternate function PORT P64/TI10/TO10, Output latch P65/TI11/TO11, (P64 to P67) P66/TI12/TO12. P67/TI13/TO13 PM64 to PM67 Alternate function Port register 6 PU6: Pull-up resistor option register 6...

  • Page 230: Port 7

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 7 Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7).
  • Page 231 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-11. Settings of Registers When Using Port 7 <R> Note 4 Pin Name PM7× POM7× Alternate Function Setting Remark Name − × Input Note 1 SCK21/SCL21 output = 1 Output × × Input Note 1...
  • Page 232 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> For example, figures 4-34 to 4-38 show block diagrams of port 7 for 128-pin products when PIOR = 00H. Figure 4-34. Block Diagram of P70 PU70 P-ch Alternate function PORT Output latch P70/KR0/SCK21/SCL21 (P70)
  • Page 233 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-35. Block Diagram of P71 PU71 P-ch Alternate function PORT Output latch P71/KR1/SI21/SDA21 (P71) POM7 POM71 PM71 Alternate function Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 POM7: Port output mode register 7 Read signal WR××: Write signal...
  • Page 234 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-36. Block Diagram of P72 PU72 P-ch Alternate function PORT Output latch P72/KR2/SO21 (P72) PM72 Alternate function Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 Read signal WR××: Write signal R01UH0146EJ0100 Rev.1.00...
  • Page 235 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-37. Block Diagram of P73, P75 to P77 PU73, PU75 to PU77 P-ch Alternate function PORT Output latch P73/KR3, (P73, P75 to P77) P75/KR5/INTP9 to P77/KR7/INTP11 PM73, PM75 to PM77 Port register 7 PU7:...
  • Page 236 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-38. Block Diagram of P74 PU74 P-ch Alternate function PORT Output latch P74/KR4/INTP8 (P74) POM7 POM74 PM74 Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 POM7: Port output mode register 7 Read signal WR××: Write signal...

  • Page 237: Port 8

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 8 Port 8 is an I/O port with an output latch. Port 8 can be set to the input mode or output mode in 1-bit units using port mode register 8 (PM8). When the P80 to P87 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 8 (PU8).
  • Page 238 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> For example, figures 4-39 to 4-41 show block diagrams of port 8 for 128-pin products when PIOR = 00H. Figure 4-39. Block Diagram of P80, P81 PIM8 PIM80, PIM81 PU80, PU81 P-ch CMOS PORT...
  • Page 239 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-40. Block Diagram of P82 PU82 P-ch PORT Output latch (P82) POM8 POM82 PM82 Port register 8 PU8: Pull-up resistor option register 8 PM8: Port mode register 8 PIM8: Port input mode register 8...
  • Page 240 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-41. Block Diagram of P83 to P87 PU83 to PU87 P-ch PORT Output latch P83 to P87 (P83 to P87) PM83 to PM87 Port register 8 PU8: Pull-up resistor option register 8 PM8: Port mode register 8 Read signal WR××: Write signal...

  • Page 241: Port 9

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.10 Port 9 Port 9 is an I/O port with an output latch. Port 9 can be set to the input mode or output mode in 1-bit units using port mode register 9 (PM9). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 9 (PU9).
  • Page 242 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-42 to 4-45 show block diagrams of port 9. Figure 4-42. Block Diagram of P90 to P94 PU90 to PU94 P-ch PORT Output latch P90 to P94 (P90 to P94) PM90 to PM94...
  • Page 243 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-43. Block Diagram of P95 PU95 P-ch Alternate function PORT Output latch P95/SCK11/SCL11 (P95) PM95 Alternate function Port register 9 PU9: Pull-up resistor option register 9 PM9: Port mode register 9 Read signal WR××: Write signal R01UH0146EJ0100 Rev.1.00...
  • Page 244 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-44. Block Diagram of P96 PU96 P-ch Alternate function PORT Output latch P96/SI11/SDA11 (P96) POM9 POM96 PM96 Alternate function Port register 9 PU9: Pull-up resistor option register 9 PM9: Port mode register 9 POM9: Port output mode register 9 Read signal WR××: Write signal...
  • Page 245 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-45. Block Diagram of P97 PU97 P-ch PORT Output latch P97/SO11 (P97) PM97 Alternate function Port register 9 PU9: Pull-up resistor option register 9 PM9: Port mode register 9 Read signal WR××: Write signal R01UH0146EJ0100 Rev.1.00...

  • Page 246: Port 10

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.11 Port 10 Port 10 is an I/O port with an output latch. Port 10 can be set to the input mode or output mode in 1-bit units using port mode register 10 (PM10). When the P100 to P106 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 10 (PU10).
  • Page 247 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-46 to 4-48 show block diagrams of port 10. Figure 4-46. Block Diagram of P100 PU10 PU100 P-ch PMC10 PMC100 PORT Output latch P100/ANI20 (P100) PM10 PM100 A/D converter P10: Port register 10...
  • Page 248 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-47. Block Diagram of P101 PU10 PU101 P-ch PORT Output latch P101 (P101) PM10 PM101 P10: Port register 10 PU10: Pull-up resistor option register 10 PM10: Port mode register 10 Read signal WR××: Write signal R01UH0146EJ0100 Rev.1.00...
  • Page 249 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-48. Block Diagram of P102 to P106 PU10 PU102 to PU106 P-ch Alternate function PORT P102/TI06/TO06, Output latch P103/TI14/TO14, (P102 to P106) P104/TI15/TO15, P105/TI16/TO16, P106/TI17/TO17 PM10 PM102 to PM106 Alternate function P10: Port register 10...

  • Page 250: Port 11

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.12 Port 11 Port 11 is an I/O port with an output latch. Port 11 can be set to the input mode or output mode in 1-bit units using port mode register 11 (PM11). When the P110 to P117 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 11 (PU11).
  • Page 251 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> For example, 4-49 and 4-50 show block diagrams of port 11 for 128-pin products when PIOR = 00H. Figure 4-49. Block Diagram of P110 to P114 PU11 PU110 to PU114 P-ch PORT Output latch...
  • Page 252 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-50. Block Diagram of P115 to P117 PU11 PU115 to PU117 P-ch PMC11 PMC115 to PMC117 PORT Output latch P115/ANI26 to (P115 to P117) P117/ANI24 PM11 PM115 to PM117 A/D converter P11: Port register 11...
  • Page 253 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.13 Port 12 P120 and P125 to 127 are an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
  • Page 254 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> For example, figures 4-51 to 4-54 show block diagrams of port 12 for 128-pin products when PIOR = 00H. Figure 4-51. Block Diagram of P120 PU12 PU120 P-ch PMC12 PMC120 PORT Output latch P120/ANI19...
  • Page 255 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> Figure 4-52. Block Diagram of P121 and P122 Clock generator OSCSEL P122/X2/EXCLK EXCLK, OSCSEL P121/X1 CMC: Clock operation mode control register Read signal R01UH0146EJ0100 Rev.1.00 Sep 22, 2011...
  • Page 256 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> Figure 4-53. Block Diagram of P123 and P124 Clock generator OSCSELS P124/XT2/EXCLKS EXCLKS, OSCSELS P123/XT1 CMC: Clock operation mode control register Read signal R01UH0146EJ0100 Rev.1.00 Sep 22, 2011...
  • Page 257 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-54. Block Diagram of P125 to P127 PU12 PU125 to PU127 P-ch PORT Output latch P125 to P127 (P125 to P127) PM12 PM125 to PM127 P12: Port register 12 PU12: Pull-up resistor option register 12...

  • Page 258: Port 13

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.14 Port 13 P130 is a 1-bit output-only port with an output latch. P137 is a 1-bit input-only port. <R> P130 is fixed an output port, and P137 is fixed an input ports. This port can also be used for external interrupt request input.
  • Page 259 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-56. Block Diagram of P137 P137/INTP0 Alternate function Read signal R01UH0146EJ0100 Rev.1.00 Sep 22, 2011...

  • Page 260: Port 14

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.15 Port 14 Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 to P147 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14).
  • Page 261 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> For example, figures 4-57 to 4-63 show block diagrams of port 14 for 128-pin products when PIOR = 00H. Figure 4-57. Block Diagram of P140 and P141 PU14 PU140, PU141 P-ch Alternate function PORT...
  • Page 262 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-58. Block Diagram of P142 PIM14 PIM142 PU14 PU142 P-ch Alternate function CMOS PORT Output latch P142/SCK30/SCL30 (P142) POM14 POM142 PM14 PM142 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14...
  • Page 263 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-59. Block Diagram of P143 PIM14 PIM143 PU14 PU143 P-ch Alternate function CMOS PORT Output latch P143/SI30/RxD3/SDA30 (P143) POM14 POM143 PM14 PM143 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14...
  • Page 264 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-60. Block Diagram of P144 PU14 PU144 P-ch PORT Output latch P144/SO30/TxD3 (P144) POM14 POM144 PM14 PM144 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14...
  • Page 265 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-61. Block Diagram of P145 PU14 PU145 P-ch Alternate function PORT Output latch P145/TI07/TO07 (P145) PM14 PM145 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 Read signal WR××: Write signal...
  • Page 266 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-62. Block Diagram of P146 PU14 PU146 P-ch PORT Output latch P146 (P146) PM14 PM146 P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 Read signal WR××: Write signal R01UH0146EJ0100 Rev.1.00...
  • Page 267 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-63. Block Diagram of P147 PU14 PU147 P-ch PMC14 PMC147 PORT Output latch P147/ANI18 (P147) PM14 PM147 A/D converter P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14...

  • Page 268: Port 15

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.16 Port 15 Port 15 is an I/O port with an output latch. Port 15 can be set to the input mode or output mode in 1-bit units using port mode register 15 (PM15). This port can also be used for A/D converter analog input.
  • Page 269 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> Figure 4-64. Block Diagram of P150 to P156 ADPC ADPC 0:Analog input 1:Digital I/O ADPC3 to ADPC0 PORT Output latch P150/ANI8 to P156/ANI14 (P150 to P156) PM15 PM150 to PM156 A/D converter ADPC: A/D port cofiguration register...

  • Page 270: Registers Controlling Port Function

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following registers. • Port mode registers (PMxx) • Port registers (Pxx) • Pull-up resistor option registers (PUxx) • Port input mode registers (PIMxx) • Port output mode registers (POMxx) •...
  • Page 271 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> Table 4-21. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (20-pin products to 64-pin products) (2/3) Port Bit name PMxx PUxx PIMxx POMxx PMCxx register register register register...
  • Page 272 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-21. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (20-pin products to 64-pin products) (3/3) Port Bit name PMxx PUxx PIMxx POMxx PMCxx register register register register register register −...
  • Page 273 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-22. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (80-pin products to 128-pin products) (1/4) Port Bit name PMxx PUxx PIMxx POMxx PMCxx register register register register register register −...
  • Page 274 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-22. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (80-pin products to 128-pin products) (2/4) Port Bit name PMxx PUxx PIMxx POMxx PMCxx register register register register register register −...
  • Page 275 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> Table 4-22. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (80-pin products to 128-pin products) (3/4) Port Bit name PMxx PUxx PIMxx POMxx PMCxx register register register register...
  • Page 276 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-22. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (80-pin products to 128-pin products) (4/4) Port Bit name PMxx PUxx PIMxx POMxx PMCxx register register register register register register −...
  • Page 277 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> For the registers mounted on others than 128-pin products, refer to table 4-21 and 4-22. (1) Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 278 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-65. Format of Port Mode Register (128-pin products) Symbol Address After reset PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 FFF20H PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FFF21H PM27 PM26 PM25 PM24...
  • Page 279 RL78/G13 CHAPTER 4 PORT FUNCTIONS (2) Port registers (Pxx) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is...
  • Page 280 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-66. Format of Port Register (128-pin products) Symbol Address After reset FFF00H 00H (output latch) R/W FFF01H 00H (output latch) R/W FFF02H 00H (output latch) R/W FFF03H 00H (output latch) R/W FFF04H 00H (output latch) R/W...
  • Page 281 RL78/G13 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode (PMmn = 1 and POMmn = 0) for the pins to which the use of an on-chip pull-up resistor has been specified in these registers.
  • Page 282 RL78/G13 CHAPTER 4 PORT FUNCTIONS (4) Port input mode registers (PIM0, PIM1, PIM4, PIM5, PIM8, PIM14) These registers set the input buffer of P01, P03, P04, P10, P11, P13 to P17, P43, P44, P53 to P55, P80, P81, P142, and P143 in 1-bit units.
  • Page 283 RL78/G13 CHAPTER 4 PORT FUNCTIONS (5) Port output mode registers (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) These registers set the output mode of P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, P142 to P144 in 1-bit units.
  • Page 284 RL78/G13 CHAPTER 4 PORT FUNCTIONS (6) Port mode control registers (PMC0, PMC3, PMC10, PMC11, PMC12, PMC14) These registers set the P00 to P03, P35 to P37, P100, P115 to P117, P120, and P147 digital I/O/analog input in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 285 RL78/G13 CHAPTER 4 PORT FUNCTIONS (7) A/D port configuration register (ADPC) This register switches the P20/ANI0 to P27/ANI7, and P150/ANI8 to P156/ANI14 pins to digital I/O of port or analog input of A/D converter. The ADPC register can be set by an 8-bit memory manipulation instruction.
  • Page 286 RL78/G13 CHAPTER 4 PORT FUNCTIONS (8) Peripheral I/O redirection register (PIOR) This register is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned.
  • Page 287 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR) Address: F0077H After reset: 00H Symbol PIOR PIOR5 PIOR4 PIOR3 PIOR2 PIOR1 PIOR0 Function 128/100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40/36/32/30-pin Setting value Setting value Setting value Setting value Setting value Setting value Setting value...
  • Page 288 RL78/G13 CHAPTER 4 PORT FUNCTIONS (9) Global digital input disable register (GDIDIS) This register is used to prevent through-current flowing from the input buffers when EV is 0 V. By setting the GDIDIS0 bit to 1, input to any input buffer connected to EV...

  • Page 289: Port Function Operations

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.

  • Page 290: Connecting To External Device With Different Potential (1.8 V, 2.5 V, 3 V)

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) <R> When parts of ports 0, 1, 4, 5, and 14 operate with V = 4.0 to 5.5 V, I/O connections with an external device that operates on 1.8 V, 2.5 V, 3 V power supply voltage are possible.
  • Page 291 RL78/G13 CHAPTER 4 PORT FUNCTIONS (b) Use as 1.8 V, 2.5 V, 3 V output port <1> Pull up externally the pin to be used (on-chip pull-up resistor cannot be used). <R> In case of UART0: In case of UART1:...

  • Page 292: Settings Of Port Mode Register, And Output Latch When Using Alternate Function

    RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.5 Settings of Port Mode Register, and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register, and output latch as shown in Table 4-23.
  • Page 293 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-23. Settings of Port Mode Register, and Output Latch When Using Alternate Function (2/5) <R> Pin Name Alternate Function PIOR× POM×× PMC×× PM×× P×× Function Name − TxD2 Output − SO20 Output − (SDAA0) ×...
  • Page 294 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> Table 4-23. Settings of Port Mode Register, and Output Latch When Using Alternate Function (3/5) Pin Name Alternate Function PIOR× POM×× PMC×× PM×× P×× Function Name − − × Note 3 INTP3 Input ×...
  • Page 295 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-23. Settings of Port Mode Register, and Output Latch When Using Alternate Function (4/5) <R> Pin Name Alternate Function PIOR× POM×× PMC×× PM×× P×× Function Name − − SCLA0 − − SDAA0 × −...
  • Page 296 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-23. Settings of Port Mode Register, and Output Latch When Using Alternate Function (5/5) <R> Pin Name Alternate Function PIOR× POM×× PMC×× PM×× P×× Function Name × − − × SCK11 Input × −...
  • Page 297 RL78/G13 CHAPTER 4 PORT FUNCTIONS Notes 1. The functions of the ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100, ANI21/P37 to ANI23/P35, and ANI24/P117 to ANI26/P115 pins can be selected by using the port mode control registers 0, 3, 10, 11, 12, 14 (PMC0, PMC3, PMC10, PMC11, PMC12, PMC14), analog input channel specification register (ADS), and port mode registers 0, 3, 10, 11, 12, 14 (PM0, PM3, PM10, PM11, PM12, PM14).

  • Page 298: Cautions When Using Port Function

    The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A 1-bit manipulation instruction is executed in the following order in the RL78/G13. <1> The Pn register is read in 8-bit units.

  • Page 299: Cautions On The Pin Settings On The Products Other Than 128-Pin

    RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> 4.6.2 Cautions on the pin settings on the products other than 128-pin In the products other than 128-pin products, multiple alternate output functions may be assigned to P15 to P17, P30 and P31 pins.
  • Page 300 RL78/G13 CHAPTER 4 PORT FUNCTIONS (6) 24- to 44-pin products: P31/TI03/TO03/INTP4/PCLBUZ0 · Using TO03: PCLBUZ0 output clear to 0 Set bit 7 (PCLOE0) of clock output select register 0 (CKS0) to “0”, which is the same as their default status setting.

  • Page 301: Chapter 5 Clock Generator

    RL78/G13 CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR The presence or absence of connecting resonator pin for main system clock, connecting resonator pin for subsystem clock, external clock input pin for main system clock, and external clock input pin for subsystem clock, depends on the product.
  • Page 302 RL78/G13 CHAPTER 5 CLOCK GENERATOR (2) Subsystem clock • XT1 clock oscillator This circuit oscillates a clock of f = 32.768 kHz by connecting a 32.768 kHz resonator to XT1 and XT2. Oscillation can be stopped by setting the XTSTOP bit (bit 6 of the clock operation status control register (CSC)).

  • Page 303: Configuration Of Clock Generator

    RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control registers Clock operation mode control register (CMC) System clock control register (CKC) Clock operation status control register (CSC)
  • Page 304 Figure 5-1. Block Diagram of Clock Generator Internal bus Clock operation mode Clock operation status Oscillation stabilization System clock control control register control register register (CKC) time select register (OSTS) (CMC) (CSC) AMPH EXCLK OSCSEL MSTOP OSTS2 OSTS1 OSTS0 MCM0 Standby controller STOP mode X1 oscillation...

  • Page 305: Registers Controlling Clock Generator

    RL78/G13 CHAPTER 5 CLOCK GENERATOR Remark f X1 clock oscillation frequency High-speed on-chip oscillator clock frequency External main system clock frequency High-speed system clock frequency : Main system clock frequency MAIN XT1 clock oscillation frequency External subsystem clock frequency : Subsystem clock frequency...
  • Page 306 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-2. Format of Clock Operation Mode Control Register (CMC) Address: FFFA0H After reset: 00H Symbol EXCLK OSCSEL EXCLKS OSCSELS AMPHS1 AMPHS0 AMPH EXCLK OSCSEL High-speed system clock X1/P121 pin X2/EXCLK/P122 pin pin operation mode...
  • Page 307 RL78/G13 CHAPTER 5 CLOCK GENERATOR • Make the wiring between the XT1 and XT2 pins and the resonators as short as possible, and minimize the parasitic capacitance and wiring resistance. Note this particularly when the ultra-low power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) is selected.
  • Page 308 RL78/G13 CHAPTER 5 CLOCK GENERATOR (2) System clock control register (CKC) <R> This register is used to select a CPU/peripheral hardware clock and a main system clock. The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 309 RL78/G13 CHAPTER 5 CLOCK GENERATOR Cautions 1. Be sure to set bit 3 to 0 to 0. 2. The clock set by the CSS bit is supplied to the CPU and peripheral hardware. If the CPU clock is changed, therefore, the clock supplied to peripheral hardware (except the real-time clock, interval timer, clock output/buzzer output, and watchdog timer) is also changed at the same time.
  • Page 310 RL78/G13 CHAPTER 5 CLOCK GENERATOR (3) Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock, high-speed on-chip oscillator clock, and subsystem clock (except the low-speed on-chip oscillator clock). The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 311 RL78/G13 CHAPTER 5 CLOCK GENERATOR Table 5-2. Stopping Clock Method Clock Condition Before Stopping Clock Setting of CSC (Invalidating External Clock Input) Register Flags CPU and peripheral hardware clocks operate with a clock X1 clock MSTOP = 1 other than the high-speed system clock.
  • Page 312 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-5. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H After reset: 00H Symbol OSTC MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST Oscillation stabilization time status...
  • Page 313 RL78/G13 CHAPTER 5 CLOCK GENERATOR (5) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation automatically waits for the time set using the OSTS register after the STOP mode is released.
  • Page 314 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H Symbol OSTS OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection = 10 MHz = 20 MHz μ μ...
  • Page 315 RL78/G13 CHAPTER 5 CLOCK GENERATOR (6) Peripheral enable register 0 (PER0) These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise.
  • Page 316 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/3) Address: F00F0H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> PER0 RTCEN IICA1EN ADCEN IICA0EN SAU1EN SAU0EN TAU1EN TAU0EN Note 1...
  • Page 317 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (3/3) Address: F00F0H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> PER0 RTCEN IICA1EN ADCEN IICA0EN SAU1EN SAU0EN TAU1EN TAU0EN Note 1...
  • Page 318 RL78/G13 CHAPTER 5 CLOCK GENERATOR (7) Operation speed mode control register (OSMC) This register is used to reduce power consumption by stopping unnecessary clock functions. If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions, except the real-time clock and interval timer, is stopped in STOP mode or HALT mode while subsystem clock is <R>...
  • Page 319 RL78/G13 CHAPTER 5 CLOCK GENERATOR (8) High-speed on-chip oscillator frequency select register (HOCODIV) The frequency of the high-speed on-chip oscillator which is set by an option byte (000C2H/0102CH) can be changed by using high-speed on-chip oscillator frequency select register (HOCODIV). However, the selectable frequency depends on the FRQSEL3 bit of the option byte (000C2H/0102CH).
  • Page 320 RL78/G13 CHAPTER 5 CLOCK GENERATOR (9) High-speed on-chip oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the high-speed on-chip oscillator. <R> With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock input (timer array unit), and so on, the accuracy can be adjusted.

  • Page 321: System Clock Oscillator

    RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
  • Page 322 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-12. Example of External Circuit of XT1 Oscillator (a) Crystal oscillation (b) External clock 32.768 EXCLKS External clock Caution 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-10 and 5-11 to avoid an adverse effect from wiring capacitance.
  • Page 323 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-13 shows examples of incorrect resonator connection. Figure 5-13. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT (c) The X1 and X2 signal line wires cross. (d) A power supply/GND pattern exists under the X1 and X2 wires.
  • Page 324 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Examples of Incorrect Resonator Connection (2/2) (e) Wiring near high alternating current (f) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (g) Signals are fetched...

  • Page 325: High-Speed On-Chip Oscillator

    5.4.3 High-speed on-chip oscillator The high-speed on-chip oscillator is incorporated in the RL78/G13. The frequency can be selected from among 32, 24, 16, 12, 8, 4, or 1 MHz by using the option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC).

  • Page 326: Clock Generator Operation

    • CPU/peripheral hardware clock f The CPU starts operation when the high-speed on-chip oscillator starts outputting after a reset release in the RL78/G13. When the power supply voltage is turned on, the clock generator operation is shown in Figure 5-14.
  • Page 327 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-14. Clock Generator Operation When Power Supply Voltage Is Turned On Power supply 1.6 V voltage (V 1.51 V (TYP.) <1> Internal reset signal Switched by software Note3 Reset processing <3> <5> <5> High-speed...

  • Page 328: Controlling Clock

    RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock 5.6.1 Example of setting high-speed on-chip oscillator After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected from 32, 24, 16, 12, 8, 4, and 1 MHz by using FRQSEL0 to FRQSEL3 of the option byte (000C2H).

  • Page 329: Example Of Setting X1 Oscillation Clock

    RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.6.2 Example of setting X1 oscillation clock After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by...

  • Page 330: Example Of Setting Xt1 Oscillation Clock

    RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.6.3 Example of setting XT1 oscillation clock After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the XT1 oscillation clock, set the oscillator and start oscillation by...

  • Page 331: Cpu Clock Status Transition Diagram

    RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.6.4 CPU clock status transition diagram Figure 5-15 shows the CPU clock status transition diagram of this product. Figure 5-15. CPU Clock Status Transition Diagram High-speed on-chip oscillator: Woken up Power ON X1 oscillation/EXCLK input: Stops (input port mode) XT1 oscillation/EXCLKS input: Stops (input port mode) <...
  • Page 332 RL78/G13 CHAPTER 5 CLOCK GENERATOR Table 5-3 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-3. CPU Clock Transition and SFR Register Setting Examples (1/5) (1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A)
  • Page 333 RL78/G13 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (2/5) (4) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Note 1 Setting Flag of SFR Register...
  • Page 334 RL78/G13 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (3/5) (6) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register...
  • Page 335 RL78/G13 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (4/5) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register OSTS...
  • Page 336 RL78/G13 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (5/5) (11) • STOP mode (H) set while CPU is operating with high-speed on-chip oscillator clock (B) • STOP mode (I) set while CPU is operating with high-speed system clock (C)

  • Page 337: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock

    RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.6.5 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-4. Changing CPU Clock (1/2) CPU Clock...
  • Page 338 RL78/G13 CHAPTER 5 CLOCK GENERATOR Table 5-5. Changing CPU Clock (2/2) CPU Clock Condition Before Change Processing After Change Before Change After Change XT1 clock High-speed on- Oscillation of high-speed on-chip oscillator XT1 oscillation can be stopped (XTSTOP = chip oscillator...

  • Page 339: Time Required For Switchover Of Cpu Clock And Main System Clock

    RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.6.6 Time required for switchover of CPU clock and main system clock By setting bits 4 and 6 (MCM0, CSS) of the system clock control register (CKC), the CPU clock can be switched (between the main system clock and the subsystem clock), and main system clock can be switched (between the high- speed on-chip oscillator clock and the high-speed system clock).

  • Page 340: Conditions Before Clock Oscillation Is Stopped

    RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.6.7 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Table 5-7. Conditions Before the Clock Oscillation Is Stopped and Flag Settings...

  • Page 341: Chapter 6 Timer Array Unit

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT CHAPTER 6 TIMER ARRAY UNIT The number of units or channels of the timer array unit differs, depending on the product. Units Channels 20, 24, 25, 30, 32, 36, 80, 100-pin 128-pin 40, 44, 48, 52, 64-pin √...
  • Page 342 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT The timer array unit has eight 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can be used to create a high-accuracy timer.

  • Page 343: Functions Of Timer Array Unit

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.1 Functions of Timer Array Unit Timer array unit has the following functions. 6.1.1 Independent channel operation function By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels.

  • Page 344: Simultaneous Channel Operation Function

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (6) Measurement of high-/low-level width of input signal Counting is started by a single edge of the signal input to the timer input pin (TImn), and the count value is captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured.

  • Page 345: 8-Bit Timer Operation Function (Channels 1 And 3 Only)

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (3) Multiple PWM (Pulse Width Modulation) output By extending the PWM function and using one master channel and two or more slave channels, up to seven types of PWM signals that have a specific period and a specified duty factor can be generated.

  • Page 346: Lin-Bus Supporting Function (Channel 7 Of Unit 0 Only)

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.1.4 LIN-bus supporting function (channel 7 of unit 0 only) Timer array unit is used to check whether signals received in LIN-bus communication match the LIN-bus communication format. (1) Detection of wakeup signal The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD2) of UART2 and the count value of the timer is captured at the rising edge.

  • Page 347: Configuration Of Timer Array Unit

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.2 Configuration of Timer Array Unit Timer array unit includes the following hardware. Table 6-1. Configuration of Timer Array Unit Item Configuration Timer/counter Timer count register mn (TCRmn) Register Timer data register mn (TDRmn)
  • Page 348 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT The presence or absence of timer I/O pins in each timer array unit channel depends on the product. <R> Table 6-2. Timer I/O Pins provided in Each Product I/O Pins of Each Product Timer array unit...
  • Page 349 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-1. Entire Configuration of Timer Array Unit 0 (Example: 64-pin products) Timer clock select register 0 (TPS0) PRS031PRS030 PRS021 PRS020 PRS013 PRS012PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 Prescaler Peripheral enable Selector Selector register 0...
  • Page 350 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-2. Internal Block Diagram of Channel of Timer Array Unit 0 Slave/master controller Trigger signal to slave channel Clock signal to slave channel Interrupt signal to slave channel CK00 Timer controller Output TCLK...
  • Page 351 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT The count value can be read by reading timer count register mn (TCRmn). The count value is set to FFFFH in the following cases. • When the reset signal is generated • When the TAUmEN bit of peripheral enable register 0 (PER0) is cleared •...
  • Page 352 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (2) Timer data register mn (TDRmn) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn).

  • Page 353: Registers Controlling Timer Array Unit

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.3 Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers. • Peripheral enable register 0 (PER0) • Timer clock select register m (TPSm) • Timer mode register mn (TMRmn) •...
  • Page 354 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (1) Peripheral enable register 0 (PER0) This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
  • Page 355 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (2) Timer clock select register m (TPSm) The TPSm register is a 16-bit register that is used to select two types or four types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel from external prescaler. CKm1 is selected by using bits 7 to 4 <R>...
  • Page 356 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-7. Format of Timer Clock Select register m (TPSm) (1/2) Address: F01B6H, F01B7H (TPS0), F01F6H, F01F7H (TPS1) After reset: 0000H Symbol TPSm Note Selection of operation clock (CKmk) (k = 0, 1) = 2 MHz...
  • Page 357 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-7. Format of Timer Clock Select register m (TPSm) (2/2) Address: F01B6H, F01B7H (TPS0), F01F6H, F01F7H (TPS1) After reset: 0000H Symbol TPSm Note Selection of operation clock (CKm2) = 2 MHz = 5 MHz f...
  • Page 358 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (3) Timer mode register mn (TMRmn) The TMRmn register sets an operation mode of channel n. This register is used to select the operation clock (f select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count).
  • Page 359 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT <R> Figure 6-8. Format of Timer Mode Register mn (TMRmn) (1/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) Symbol TMRmn MAST ERmn (n = 2, 4, 6 )
  • Page 360 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT <R> Figure 6-8. Format of Timer Mode Register mn (TMRmn) (2/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) Symbol TMRmn MAST ERmn (n = 2, 4, 6 )
  • Page 361 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT <R> Figure 6-8. Format of Timer Mode Register mn (TMRmn) (3/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) Symbol TMRmn MAST ERmn (n = 2, 4, 6 )
  • Page 362 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT <R> Figure 6-8. Format of Timer Mode Register mn (TMRmn) (4/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) Symbol TMRmn MAST ERmn (n = 2, 4, 6 )
  • Page 363 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (4) Timer status register mn (TSRmn) The TSRmn register indicates the overflow status of the counter of channel n. The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode (MDmn3 to MDmn1 = 110B).
  • Page 364 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (5) Timer channel enable status register m (TEm) The TEm register is used to enable or stop the timer operation of each channel. Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer <R>...
  • Page 365 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (6) Timer channel start register m (TSm) <R> The TSm register is a trigger register that is used to initialize timer count register mn (TCRmn) and start the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is set to 1.
  • Page 366 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (7) Timer channel stop register m (TTm) The TTm register is a trigger register that is used to stop the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is cleared to 0.
  • Page 367 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (8) Timer input select register 0 (TIS0) The TIS0 register is used to select the channel 5 of unit 0 timer input.. The TIS0 register can be set by an 8-bit memory manipulation instruction.
  • Page 368 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (9) Timer output enable register m (TOEm) The TOEm register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer output register m (TOm) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TOmn).
  • Page 369 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (10) Timer output register m (TOm) The TOm register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TOmn) of each channel.
  • Page 370 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (11) Timer output level register m (TOLm) The TOLm register is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOEmn = 1) in the Slave channel output mode (TOMmn = 1).
  • Page 371 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (12) Timer output mode register m (TOMm) The TOMm register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0.
  • Page 372 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (13) Input switch control register (ISC) The ISC1 and ISC0 bits of the ISC register are used to implement LIN-bus communication operation by using channel 7 in association with the serial array unit. When the ISC1 bit is set to 1, the input signal of the serial data input pin (RxD2) is selected as a timer input signal.
  • Page 373 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (14) Noise filter enable registers 1, 2 (NFEN1, NFEN2) The NFEN1, NFEN2 registers is used to set whether the noise filter can be used for the timer input signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
  • Page 374 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-19. Format of Noise Filter Enable Registers 1, 2 (NFEN1, NFEN2) (1/2) Address: F0071H After reset: 00H Symbol NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00 Address: F0072H After reset: 00H Symbol...
  • Page 375 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-19. Format of Noise Filter Enable Registers 1, 2 (NFEN1, NFEN2) (2/2) Address: F0071H After reset: 00H Symbol NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00 Address: F0072H After reset: 00H Symbol...
  • Page 376 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (15) Port mode registers 0, 1, 3, 4, 6, 10, 14 (PM0, PM1, PM3, PM4, PM6, PM10, PM14) These registers set input/output of ports 0, 1, 3, 4, 6, 10, 14 in 1-bit units.
  • Page 377 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-20. Format of Port Mode Registers 0, 1, 3, 4, 6, 10, 14 (PM0, PM1, PM3, PM4, PM6, PM10, PM14) (128-pin products) Address: FFF20H After reset: FFH Symbol PM06 PM05 PM04 PM03 PM02...

  • Page 378: Basic Rules Of Timer Array Unit

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.4 Basic Rules of Timer Array Unit 6.4.1 Basic rules of simultaneous channel operation function When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.
  • Page 379 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Example TAU0 Channel group 1 CKm0 Channel 0: Master (Simultaneous channel operation function) Channel 1: Slave Channel group 2 Channel 2: Slave (Simultaneous channel operation function) Channel 3: independent channel operation function * The operating clock of channel group 1 may CKm1 be different from that of channel group 2.

  • Page 380: Basic Rules Of 8-Bit Timer Operation Function (Channels 1 And 3 Only)

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8- bit timer channels.

  • Page 381: Operation Timing Of Counter

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.5 Operation Timing of Counter 6.5.1 Count clock (f TCLK The count clock (f ) of the timer array unit can be selected between following by CCSmn bit of timer mode register TCLK mn (TMRmn). .
  • Page 382 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) The count clock (f ) becomes the signal that detects valid edge of input signal via the TImn pin and synchronizes...

  • Page 383: Start Timing Of Counter

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.5.2 Start timing of counter Timer count register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start register m (TSm). Operations from count operation enabled state to timer count Register mn (TCRmn) count start is shown in Table 6-6.
  • Page 384 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (a) Start timing in interval timer mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. Timer count register mn (TCRmn) holds the initial value until count clock generation.
  • Page 385 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (b) Start timing in event counter mode <1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0). <2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
  • Page 386 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (c) Start timing in capture mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until count clock generation.
  • Page 387 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (d) Start timing in one-count mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.
  • Page 388 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (e) Start timing in capture & one-count mode (when high-level width is measured) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm).

  • Page 389: Channel Output (Tomn Pin) Control

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.6 Channel Output (TOmn pin) Control 6.6.1 TOmn pin output circuit configuration Figure 6-28. Output Circuit Configuration <5> TOmn register Interrupt signal of the master channel (INTTMmn) TOmn pin Interrupt signal of the slave channel...

  • Page 390: Tomn Pin Output Setting

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.6.2 TOmn Pin Output Setting The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer operation start. Figure 6-29. Status Transition from Timer Output Setting to Operation Start...

  • Page 391: Cautions On Channel Output Operation

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.6.3 Cautions on Channel Output Operation (1) Changing values set in the registers TOm, TOEm, TOLm, and TOMm during timer operation Since the timer operations (operations of timer count register mn (TCRmn) and timer data register mn (TDRmn)) are...
  • Page 392 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (2) Default level of TOmn pin and output level after timer operation start The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer output is disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1) before port output is enabled, is shown below.
  • Page 393 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (b) When operation starts with slave channel output mode (TOMmn = 1) setting (PWM output)) When slave channel output mode (TOMmn = 1), the active level is determined by timer output level register m (TOLm) setting.
  • Page 394 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (3) Operation of TOmn pin in slave channel output mode (TOMmn = 1) (a) When timer output level register m (TOLm) setting has been changed during timer operation When the TOLm register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TOmn pin change condition.
  • Page 395 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (b) Set/reset timing To realize 0%/100% output at PWM output, the TOmn pin/TOmn bit set timing at master channel timer interrupt (INTTMmn) generation is delayed by 1 count clock by the slave channel. If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
  • Page 396 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-33. Set/Reset Timing Operating Statuses (1) Basic operation timing TCLK INTTMmn Internal reset Master signal channel TOmn pin/ TOmn Toggle Toggle Internal set signal 1 clock delay INTTMmp Slave channel Internal reset signal...

  • Page 397: Collective Manipulation Of Tomn Bit

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.6.4 Collective manipulation of TOmn bit In timer output register m (TOm), the setting bits for all the channels are located in one register in the same way as timer channel start register m (TSm). Therefore, the TOmn bit of all the channels can be manipulated collectively.

  • Page 398: Timer Interrupt And Tomn Pin Output At Operation Start

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Caution While timer output is enabled (TOEmn = 1), even if the output by timer interrupt of each timer (INTTMmn) contends with writing to the TOmn bit, output is normally done to the TOmn pin.

  • Page 399: Independent Channel Operation Function Of Timer Array Unit

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.7 Independent Channel Operation Function of Timer Array Unit 6.7.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals.
  • Page 400 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-37. Block Diagram of Operation as Interval Timer/Square Wave Output CKm1 Note Operation clock Timer counter Output CKm0 TOmn pin register mn (TCRmn) controller Interrupt Timer data Interrupt signal TSmn controller register mn(TDRmn) (INTTMmn) <R>...
  • Page 401 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-39. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/2) (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2...
  • Page 402 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-39. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/2) (d) Timer output level register m (TOLm) Bit n TOLm 0: Cleared to 0 when TOMmn = 0 (master channel output mode)
  • Page 403 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-40. Operation Procedure of Interval Timer/Square Wave Output Function (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 Power-on status.
  • Page 404 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-40. Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Software Operation Hardware Status To hold the TOmn pin output level Clears the TOmn bit to 0 after the value to stop be held is set to the port register.

  • Page 405: Operation As External Event Counter

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.7.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an interrupt.
  • Page 406 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-42. Example of Basic Timing of Operation as External Event Counter TSmn TEmn TImn TCRmn 0000H TDRmn 0003H 0002H INTTMmn 4 events 4 events 3 events Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) 2.
  • Page 407 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Example of Set Contents of Registers in External Event Counter Mode (1/2) (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0...
  • Page 408 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Example of Set Contents of Registers in External Event Counter Mode (2/2) (d) Timer output level register m (TOLm) Bit n TOLm 0: Cleared to 0 when TOMmn = 0 (master channel output mode).
  • Page 409 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Operation Procedure When External Event Counter Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.

  • Page 410: Operation As Frequency Divider (Channel 0 Of Unit 0 Only)

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.7.3 Operation as frequency divider (channel 0 of unit 0 only) The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the result from the TO00 pin.
  • Page 411 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-46. Example of Basic Timing of Operation as Frequency Divider (MD000 = 1) TS00 TE00 TI00 TCR00 0000H TDR00 0002H 0001H TO00 INTTM00 Divided Divided by 6 by 4 Remark TS00: Bit n of timer channel start register 0 (TS0)
  • Page 412 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Example of Set Contents of Registers During Operation as Frequency Divider (a) Timer mode register 00 (TMR00) TMR00 CKS0n1 CKS0n0 CCS00 STS002 STS001 STS000 CIS001 CIS000 MD003 MD002 MD001 MD000 TER00 Operation mode of channel 0...
  • Page 413 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-48. Operation Procedure When Frequency Divider Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1.

  • Page 414: Operation As Input Pulse Interval Measurement

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.7.4 Operation as input pulse interval measurement The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured. The pulse interval can be calculated by the following expression.
  • Page 415 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-50. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0 = 0) TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn 0000H INTTMmn Remarks 1. m: Unit number (m = 0, 1)n: Channel number (n = 0 to 7) 2.
  • Page 416 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-51. Example of Set Contents of Registers to Measure Input Pulse Interval (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n...
  • Page 417 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-52. Operation Procedure When Input Pulse Interval Measurement Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.

  • Page 418: Operation As Input Signal High-/Low-Level Width Measurement

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.7.5 Operation as input signal high-/low-level width measurement Caution When using a channel to implement the LIN-bus, set bit 1 (ISC1) of the input switch control register (ISC) to 1. In the following descriptions, read TImn as RxD2.
  • Page 419 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-53. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement CKm1 Note Operation clock CKm0 Timer counter register mn (TCRmn) Timer data Interrupt Edge Interrupt signal TImn pin register mn (TDRmn) controller...
  • Page 420 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-55. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n 110B: Capture &...
  • Page 421 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-56. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 Power-on status.

  • Page 422: Operation As Delay Counter

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.7.6 Operation as delay counter It is possible to start counting down when the valid edge of the TImn pin input is detected (an external event), and then generate INTTMmn (a timer interrupt) after any specified interval.
  • Page 423 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-58. Example of Basic Timing of Operation as Delay Counter TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn INTTMmn Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) 2.
  • Page 424 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Example of Set Contents of Registers to Delay Counter (1/2) (a) Timer mode register mn (TMRmn) Note TMRmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n...
  • Page 425 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Example of Set Contents of Registers to Delay Counter (2/2) (d) Timer output level register m (TOLm) Bit n TOLm 0: Cleared to 0 when TOMmn = 0 (master channel output mode).
  • Page 426 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-60. Operation Procedure When Delay Counter Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 Power-on status.

  • Page 427: Simultaneous Channel Operation Function Of Timer Array Unit

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.8 Simultaneous Channel Operation Function of Timer Array Unit 6.8.1 Operation as one-shot pulse output function By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the TImn pin.
  • Page 428 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-61. Block Diagram of Operation as One-Shot Pulse Output Function Master channel (one-count mode) CKm1 Operation clock Timer counter register mn (TCRmn) CKm0 TSmn Timer data Interrupt Interrupt signal register mn (TDRmn) controller...
  • Page 429 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-62. Example of Basic Timing of Operation as One-Shot Pulse Output Function TSmn TEmn TImn Master FFFFH channel TCRmn 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel TDRmp TOmp INTTMmp Remarks 1.
  • Page 430 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel) (a) Timer mode register mn (TMRmn) TMRmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2...
  • Page 431 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel) (a) Timer mode register mp (TMRmp) TMRmp Note CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3...
  • Page 432 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Operation Procedure of One-Shot Pulse Output Function (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable registers 0 Power-on status.
  • Page 433 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Operation Procedure of One-Shot Pulse Output Function (2/2) Software Operation Hardware Status Operation Sets the TOEmp bit (slave) to 1 (only when operation is start resumed). The TSmn (master) and TSmp (slave) bits of timer channel start register m (TSm) are set to 1 at the same time.

  • Page 434: Operation As Pwm Function

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.8.2 Operation as PWM function Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions.
  • Page 435 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-66. Block Diagram of Operation as PWM Function Master channel (interval timer mode) CKm1 Operation clock Timer counter register mn (TCRmn) CKm0 Timer data Interrupt Interrupt signal TSmn register mn (TDRmn) controller (INTTMmn)
  • Page 436 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. Example of Basic Timing of Operation as PWM Function TSmn TEmn FFFFH Master TCRmn channel 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel TDRmp TOmp INTTMmp Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n <...
  • Page 437 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used (a) Timer mode register mn (TMRmn) TMRmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0...
  • Page 438 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used (a) Timer mode register mp (TMRmp) TMRmp Note CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3 MDmp2 MDmp1...
  • Page 439 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-70. Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 Power-on status.
  • Page 440 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-70. Operation Procedure When PWM Function Is Used (2/2) Software Operation Hardware Status Operation Sets the TOEmp bit (slave) to 1 (only when operation is start resumed). The TSmn (master) and TSmp (slave) bits of timer...

  • Page 441: Operation As Multiple Pwm Output Function

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.8.3 Operation as multiple PWM output function By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values can be output. For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the following expressions.
  • Page 442 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-71. Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs) Master channel (interval timer mode) CKm1 Operation clock Timer counter register mn (TCRmn) CKm0 Timer data Interrupt Interrupt signal...
  • Page 443 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-72. Example of Basic Timing of Operation as Multiple PWM Output Function (Output two types of PWMs) (1/2) TSmn TEmn FFFFH Master TCRmn channel 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave...
  • Page 444 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-72. Example of Basic Timing of Operation as Multiple PWM Output Function (Output two types of PWMs) (2/2) Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n <...
  • Page 445 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Example of Set Contents of Registers When Multiple PWM Output Function (Master Channel) Is Used (a) Timer mode register mn (TMRmn) TMRmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2...
  • Page 446 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Example of Set Contents of Registers When Multiple PWM Output Function (Slave Channel) Is Used (output two types of PWMs) (a) Timer mode register mp, mq (TMRmp, TMRmq) Note TMRmp CKSmp1 CKSmp0...
  • Page 447 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-75. Operation Procedure When Multiple PWM Output Function Is Used (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
  • Page 448 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-75. Operation Procedure When Multiple PWM Output Function Is Used (2/2) Software Operation Hardware Status Operation (Sets the TOEmp and TOEmq (slave) bits to 1 only when start resuming operation.) The TSmn bit (master), and TSmp and TSmq (slave) bits...

  • Page 449: Cautions When Using Timer Array Unit

    RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Cautions When Using Timer Array Unit <R> 6.9.1 Cautions When Using Timer output Depends on products, a pin is assigned atimer output and other alternate functions. In this case, outputs of the other alternate functions must be set in initial status.

  • Page 450: Chapter 7 Real-Time Clock

    RL78/G13 CHAPTER 7 REAL-TIME CLOCK CHAPTER 7 REAL-TIME CLOCK 7.1 Functions of Real-time Clock The real-time clock has the following features. • Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years.
  • Page 451 RL78/G13 CHAPTER 7 REAL-TIME CLOCK Figure 7-1. Block Diagram of Real-time Clock Real-time clock control register 1 Real-time clock control register 0 Operation speed mode WUTMM WALE WALIE WAFG RIFG RWST RWAIT RTCE RCLOE1 AMPM control register (OSMC) RTC1HZ Alarm week...

  • Page 452: Registers Controlling Real-Time Clock

    RL78/G13 CHAPTER 7 REAL-TIME CLOCK 7.3 Registers Controlling Real-time Clock The real-time clock is controlled by the following registers. • Peripheral enable register 0 (PER0) • Operation speed mode control register (OSMC) • Real-time clock control register 0 (RTCC0) • Real-time clock control register 1 (RTCC1) •...
  • Page 453 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (1) Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
  • Page 454 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (2) Operation speed mode control register (OSMC) The WUTMMCK0 bit can be used to select the real-time clock operation clock (f In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power consumption.
  • Page 455 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (3) Real-time clock control register 0 (RTCC0) The RTCC0 register is an 8-bit register that is used to start or stop the real-time clock operation, control the RTC1HZ pin, and set a 12- or 24-hour system and the constant-period interrupt function.
  • Page 456 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (4) Real-time clock control register 1 (RTCC1) The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the counter. The RTCC1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 457 RL78/G13 CHAPTER 7 REAL-TIME CLOCK Figure 7-5. Format of Real-time Clock Control Register 1 (RTCC1) (2/2) RIFG Constant-period interrupt status flag Constant-period interrupt is not generated. Constant-period interrupt is generated. This flag indicates the status of generation of the constant-period interrupt. When the constant-period interrupt is generated, it is set to “1”.
  • Page 458 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (5) Second count register (SEC) The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of seconds. It counts up when the sub-count register overflows.
  • Page 459 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (7) Hour count register (HOUR) The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and indicates the count value of hours.
  • Page 460 RL78/G13 CHAPTER 7 REAL-TIME CLOCK Table 7-2 shows the relationship between the setting value of the AMPM bit, the hour count register (HOUR) value, and time. Table 7-2. Displayed Time Digits 24-Hour Display (AMPM = 1) 12-Hour Display (AMPM = 1)
  • Page 461 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (8) Day count register (DAY) The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows.
  • Page 462 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (9) Week count register (WEEK) The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of weekdays. It counts up in synchronization with the day counter.
  • Page 463 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (10) Month count register (MONTH) The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows.
  • Page 464 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (12) Watch error correction register (SUBCUD) This register is used to correct the watch with high accuracy when it is slow or fast by changing the value that overflows from the sub-count register to the second count register (SEC) (reference value: 7FFFH).
  • Page 465 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (13) Alarm minute register (ALARMWM) This register is used to set minutes of alarm. The ALARMWM register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Caution Set a decimal value of 00 to 59 to this register in BCD code.
  • Page 466 RL78/G13 CHAPTER 7 REAL-TIME CLOCK Here is an example of setting the alarm. Time of Alarm 12-Hour Display 24-Hour Display Sunday Monday Friday Hour Hour Minute Minute Hour Hour Minute Minute Tuesday Saturday Thursday Wednesday Every day, 0:00 a.m. Every day, 1:30 a.m.

  • Page 467: Real-Time Clock Operation

    RL78/G13 CHAPTER 7 REAL-TIME CLOCK 7.4 Real-time Clock Operation 7.4.1 Starting operation of real-time clock Figure 7-17. Procedure for Starting Operation of Real-time Clock Start Note 1 RTCEN = 1 Supplies input clock. RTCE = 0 Stops counter operation. Setting WUTMMCK0...

  • Page 468: Shifting To Stop Mode After Starting Operation

    RL78/G13 CHAPTER 7 REAL-TIME CLOCK 7.4.2 Shifting to STOP mode after starting operation Perform one of the following processing when shifting to STOP mode immediately after setting the RTCE bit to 1. However, after setting the RTCE bit to 1, this processing is not required when shifting to STOP mode after the INTRTC interrupt has occurred.

  • Page 469: Reading/Writing Real-Time Clock

    RL78/G13 CHAPTER 7 REAL-TIME CLOCK 7.4.3 Reading/writing real-time clock Read or write the counter after setting 1 to RWAIT first. Set RWAIT to 0 after completion of reading or writing the counter. <R> Figure 7-19. Procedure for Reading Real-time Clock Start Stops SEC to YEAR counters.
  • Page 470 RL78/G13 CHAPTER 7 REAL-TIME CLOCK Figure 7-20. Procedure for Writing Real-time Clock Start Stops SEC to YEAR counters. RWAIT = 1 Mode to read and write count values RWST = 1? Checks wait status of counter. Writing SEC Writes second count register.

  • Page 471: Setting Alarm Of Real-Time Clock

    RL78/G13 CHAPTER 7 REAL-TIME CLOCK 7.4.4 Setting alarm of real-time clock Set time of alarm after setting 0 to WALE (alarm operation invalid.) first. Figure 7-21. Alarm processing Procedure Start Match operation of alarm is invalid. WALE = 0 alarm match interrupts is valid..

  • Page 472: Hz Output Of Real-Time Clock

    RL78/G13 CHAPTER 7 REAL-TIME CLOCK 7.4.5 1 Hz output of real-time clock Figure 7-22. 1 Hz Output Setting Procedure Start RTCE = 0 Stops counter operation. Setting port Sets P30 and PM30 <R> RCLOE1 = 1 Enables output of the RTC1HZ pin (1 Hz).

  • Page 473: Example Of Watch Error Correction Of Real-Time Clock

    RL78/G13 CHAPTER 7 REAL-TIME CLOCK 7.4.6 Example of watch error correction of real-time clock The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction register. Example of calculating the correction value The correction value used when correcting the count value of the sub-count register is calculated by using the following expression.
  • Page 474 RL78/G13 CHAPTER 7 REAL-TIME CLOCK Correction example Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm) [Measuring the oscillation frequency] Note The oscillation frequency of each product is measured by outputting about 1 Hz from the RTC1HZ pin when the watch error correction register (SUBCUD) is set to its initial value (00H).
  • Page 475 Figure 7-23. Operation when (DEV, F6, F5, F4, F3, F2, F1, F0) = (1, 1, 1, 0, 1, 1, 1, 0) 7FFFH + 56H (86) 7FFFH + 56H (86) 7FFFH + 56H (86) 7FFFH+56H (86) Count start Sub-count register 0000H 8054H 8055H 0000H 0001H 7FFFH...

  • Page 476: Chapter 8 Interval Timer

    RL78/G13 CHAPTER 8 INTERVAL TIMER CHAPTER 8 INTERVAL TIMER 8.1 Functions of Interval Timer An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from STOP <R> mode and triggering an A/D converter’s SNOOZE mode.

  • Page 477: Registers Controlling Interval Timer

    RL78/G13 CHAPTER 8 INTERVAL TIMER 8.3 Registers Controlling Interval Timer The interval timer is controlled by the following registers. • Peripheral enable register 0 (PER0) • Operation speed mode control register (OSMC) • Interval timer control register (ITMC) (1) Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware.
  • Page 478 RL78/G13 CHAPTER 8 INTERVAL TIMER (2) Operation speed mode control register (OSMC) The WUTMMCK0 bit can be used to select the interval timer operation clock. In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power consumption.
  • Page 479 RL78/G13 CHAPTER 8 INTERVAL TIMER (3) Interval timer control register (ITMC) This register is used to set up the starting and stopping of the interval timer operation and to specify the timer compare value. The ITMC register can be set by a 16-bit memory manipulation instruction.

  • Page 480: Interval Timer Operation

    RL78/G13 CHAPTER 8 INTERVAL TIMER 8.4 Interval Timer Operation The count value specified for the ITCMP11 to ITCMP0 bits is used as an interval to operate an interval timer that repeatedly generates interrupt requests (INTIT). When the RINTE bit is set to 1, the 12-bit counter starts counting.

  • Page 481: Chapter 9 Clock Output/Buzzer Output Controller

    RL78/G13 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER The number of output pins of the clock output and buzzer output controllers differs, depending on the product. Output pin 20-pin 24, 25-pin 30, 32, 36, 40, 44, 48, 52, 64, 80, 100, 128-pin −...
  • Page 482 RL78/G13 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 9-1. Block Diagram of Clock Output/Buzzer Output Controller Internal bus Clock output select register 1 (CKS1) PCLOE1 CSEL1 CCS12 CCS11 CCS10 MAIN Prescaler PCLOE1 to f MAIN MAIN Clock/buzzer to f Note...

  • Page 483: Configuration Of Clock Output/Buzzer Output Controller

    RL78/G13 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 9-1. Configuration of Clock Output/Buzzer Output Controller Item Configuration Control registers Clock output select registers n (CKSn)
  • Page 484 RL78/G13 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 9-2. Format of Clock Output Select Register n (CKSn) Address: FFFA5H (CKS0), FFFA6H (CKS1) After reset: 00H Symbol <7> CKSn PCLOEn CSELn CCSn2 CCSn1 CCSn0 PCLOEn PCLBUZn pin output enable/disable specification Output disable (default)
  • Page 485 RL78/G13 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (2) Port mode register 1, 3, 5, 14 (PM1, PM3, PM5, PM14) <R> These registers set input/output of port in 1-bit units. For example in 64-pin products, when using the P140/INTP6/PCLBUZ0 and P141/INTP7/PCLBUZ1 pins for clock output and buzzer output clear PM140 and PM141 bits and the output latches of P140 and P141 to 0.

  • Page 486: Operations Of Clock Output/Buzzer Output Controller

    RL78/G13 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.4 Operations of Clock Output/Buzzer Output Controller One pin can be used to output a clock or buzzer sound. The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0).

  • Page 487: Chapter 10 Watchdog Timer

    RL78/G13 CHAPTER 10 WATCHDOG TIMER CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer The watchdog timer operates on the low-speed on-chip oscillator clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated.

  • Page 488: Configuration Of Watchdog Timer

    RL78/G13 CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 10-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option byte.

  • Page 489: Register Controlling Watchdog Timer

    RL78/G13 CHAPTER 10 WATCHDOG TIMER 10.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again.

  • Page 490: Operation Of Watchdog Timer

    RL78/G13 CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Controlling operation of watchdog timer When the watchdog timer is used, its operation is specified by the option byte (000C0H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 24).

  • Page 491: Setting Overflow Time Of Watchdog Timer

    RL78/G13 CHAPTER 10 WATCHDOG TIMER <R> Cautions 4. The operation of the watchdog timer in the HALT and STOP and SNOOZE modes differs as follows depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H). WDSTBYON = 0...

  • Page 492: Setting Window Open Period Of Watchdog Timer

    RL78/G13 CHAPTER 10 WATCHDOG TIMER 10.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (000C0H). The outline of the window is as follows.

  • Page 493: Setting Watchdog Timer Interval Interrupt

    RL78/G13 CHAPTER 10 WATCHDOG TIMER Remark If the overflow time is set to 2 , the window close time and open time are as follows. Setting of Window Open Period 100% Window close time 0 to 20.08 ms 0 to 10.04 ms...

  • Page 494: Chapter 11 A/D Converter

    RL78/G13 CHAPTER 11 A/D CONVERTER CHAPTER 11 A/D CONVERTER The number of analog input channels of the A/D converter differs, depending on the product. 20, 24, 25-pin 30, 32-pin 36-pin 40-pin 44, 48-pin 52, 64-pin 80-pin 100-pin 128-pin Analog 6 ch...
  • Page 495 RL78/G13 CHAPTER 11 A/D CONVERTER <R> Figure 11-1. Block Diagram of A/D Converter Internal bus A/D port configuration A/D test register register (ADPC) (ADTES) Conversion result Conversion result ADPC3 ADPC2 ADPC1 ADPC0 ADTES1 ADTES0 comparison upper limit comparison lower limit...

  • Page 496: Configuration Of A/D Converter

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI14 and ANI16 to ANI26 pins <R> These are the analog input pins of the 26 channels of the A/D converter. They input analog signals to be converted into digital signals.
  • Page 497 RL78/G13 CHAPTER 11 A/D CONVERTER (5) Successive approximation register (SAR) <R> The SAR register is a register that sets voltage tap data whose values from the comparison voltage generator match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB).

  • Page 498: Registers Used In A/D Converter

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.3 Registers Used in A/D Converter The A/D converter uses the following registers. • Peripheral enable register 0 (PER0) • A/D converter mode register 0 (ADM0) • A/D converter mode register 1 (ADM1) • A/D converter mode register 2 (ADM2) •...
  • Page 499 RL78/G13 CHAPTER 11 A/D CONVERTER (1) Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
  • Page 500 RL78/G13 CHAPTER 11 A/D CONVERTER (2) A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 501 RL78/G13 CHAPTER 11 A/D CONVERTER Table 11-1. Settings of ADCS and ADCE Bits ADCS ADCE A/D Conversion Operation Stop status (DC power consumption path does not exist) Note Conversion standby mode (only A/D voltage comparator consumes power Setting prohibited Conversion mode (A/D voltage comparator: enables operation) <R>...
  • Page 502 RL78/G13 CHAPTER 11 A/D CONVERTER Figure 11-4. Timing Chart When A/D Voltage Comparator Is Used A/D voltage comparator: enables operation ADCE A/D voltage comparator Conversion Conversion Conversion Conversion operation stopped standby standby Software ADCS Note trigger mode 1 is written 0 is written to ADCS.
  • Page 503 RL78/G13 CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (1/8) (1) 3.6 V ≤ V ≤ 5.5 V When there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Register 0 (ADM0) Mode...
  • Page 504 RL78/G13 CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (2/8) (2) 2.7 V ≤ V < 3.6 V when there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Register 0 (ADM0) Mode...
  • Page 505 RL78/G13 CHAPTER 11 A/D CONVERTER <R> Table 11-3. A/D Conversion Time Selection (3/8) (3) 1.8 V ≤ V < 2.7 V when there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Register 0 (ADM0)
  • Page 506 RL78/G13 CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (4/8) <R> (4) 1.6 V ≤ V < 2.7 V when there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Register 0 (ADM0)
  • Page 507 RL78/G13 CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (5/8) (5) 3.6 V ≤ V ≤ 5.5 V when there is stabilization wait time (hardware trigger wait mode) A/D Converter Mode Register 0 (ADM0) Mode Conversion Time Selection...
  • Page 508 RL78/G13 CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (6/8) (6) 2.7 V ≤ V < 3.6 V when there is stabilization wait time (hardware trigger wait mode) A/D Converter Mode Register 0 (ADM0) Mode Conversion Time Selection...
  • Page 509 RL78/G13 CHAPTER 11 A/D CONVERTER <R> Table 11-3. A/D Conversion Time Selection (7/8) (7) 1.8 V ≤ V < 2.7 V when there is stabilization wait time (hardware trigger wait mode) A/D Converter Mode Register 0 (ADM0) Mode Conversion Time Selection...
  • Page 510 RL78/G13 CHAPTER 11 A/D CONVERTER <R> Table 11-3. A/D Conversion Time Selection (8/8) (8) 1.6 V ≤ V < 1.8 V When there is stabilization wait time (hardware trigger wait mode) A/D Converter Mode Register 0 (ADM0) Mode Conversion Time Selection...
  • Page 511 RL78/G13 CHAPTER 11 A/D CONVERTER Figure 11-5. A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode) ← ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Sampling Successive conversion Sampling Transfer clear to ADCR, clear INTAD generation...
  • Page 512 RL78/G13 CHAPTER 11 A/D CONVERTER (4) A/D converter mode register 2 (ADM2) This register is used to select the A/D converter reference voltage, check the upper limit and lower limit A/D conversion result values, select the resolution, and specify whether to use the SNOOZE mode.
  • Page 513 RL78/G13 CHAPTER 11 A/D CONVERTER Figure 11-7. Format of A/D Converter Mode Register 2 (ADM2) (2/2) Address: F0010H After reset: 00H Symbol <3> <2> <0> ADM2 ADREFP1 ADREFP0 ADREFM ADRCK ADTYP Specification of the SNOOZE mode Do not use the SNOOZE mode function.
  • Page 514 RL78/G13 CHAPTER 11 A/D CONVERTER (5) 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result in the select mode. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR).
  • Page 515 RL78/G13 CHAPTER 11 A/D CONVERTER (7) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 516 RL78/G13 CHAPTER 11 A/D CONVERTER Figure 11-11. Format of Analog Input Channel Specification Register (ADS) (2/2) <R> Address: FFF31H After reset: 00H Symbol ADISS ADS4 ADS3 ADS2 ADS1 ADS0 Scan mode (ADMD = 1) ADISS ADS4 ADS3 ADS2 ADS1 ADS0...
  • Page 517 RL78/G13 CHAPTER 11 A/D CONVERTER (8) Conversion result comparison upper limit setting register (ADUL) This register is used to specify the setting for checking the upper limit of the A/D conversion results. The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 11-8).
  • Page 518 RL78/G13 CHAPTER 11 A/D CONVERTER (10) A/D test register (ADTES) This register is used to select the + side reference voltage (AV ) or - side reference voltage (AV ) of the A/D REFP REFM converter, or the analog input channel (ANIxx) as the A/D conversion target for the A/D test function.
  • Page 519 RL78/G13 CHAPTER 11 A/D CONVERTER (11) A/D port configuration register (ADPC) <R> This register switches the ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI14/P156 pins to analog input of A/D converter or digital I/O of port. The ADPC register can be set by an 8-bit memory manipulation instruction.
  • Page 520 RL78/G13 CHAPTER 11 A/D CONVERTER <R> (12) Port mode control registers 0, 3, 10, 11, 12, 14 (PMC0, PMC3, PMC10, PMC11, PMC12, PMC14) This register switches the ANI16 to ANI26 pins to digital I/O of port or analog input of A/D converter.
  • Page 521 RL78/G13 CHAPTER 11 A/D CONVERTER (13) Port mode register 0, 2, 3, 10, 11, 12, 14, 15 (PM0, PM2, PM3, PM10, PM11, PM12, PM14, PM15) <R> When using the ANI0 to ANI14 or ANI16 to ANI26 pin for an analog input port, set the PMmn bit to 1. The output latches of Pnm at this time may be 0 or 1.
  • Page 522 RL78/G13 CHAPTER 11 A/D CONVERTER The ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI14/P156 pins are as shown below depending on the settings of the <R> A/D port configuration register (ADPC), analog input channel specification register (ADS), PM2 and PM15 registers.

  • Page 523: A/D Converter Conversion Operations

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended.
  • Page 524 RL78/G13 CHAPTER 11 A/D CONVERTER Figure 11-18. Conversion Operation of A/D Converter (Software Trigger Mode) ← ADCS 1 or ADS rewrite Conversion time Sampling time A/D converter SAR clear Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.

  • Page 525: Input Voltage And Conversion Results

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI14, ANI16 to ANI26) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.

  • Page 526: A/D Converter Operation Modes

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.6 A/D Converter Operation Modes The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is described in 11.7 A/D Converter Setup Flowchart. 11.6.1 Software trigger mode (select mode, sequential conversion mode) <1>...

  • Page 527: Software Trigger Mode (Select Mode, One-Shot Conversion Mode)

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.2 Software trigger mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the <R> A/D conversion standby status.

  • Page 528: Software Trigger Mode (Scan Mode, Sequential Conversion Mode)

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.3 Software trigger mode (scan mode, sequential conversion mode) <R> <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 529: Software Trigger Mode (Scan Mode, One-Shot Conversion Mode)

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.4 Software trigger mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the <R> A/D conversion standby status.

  • Page 530: Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) <R> <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 531: Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode)

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode) <R> <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 532: Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) <R> <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 533: Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode)

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the <R>...

  • Page 534: Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) <R> <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.

  • Page 535: Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the <R>...

  • Page 536: Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the <R>...

  • Page 537: Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode)

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) <R> <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 538: A/D Converter Setup Flowchart

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.7 A/D Converter Setup Flowchart The A/D converter setup flowchart in each operation mode is described below. R01UH0146EJ0100 Rev.1.00 Sep 22, 2011...

  • Page 539: Setting Up Software Trigger Mode

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.7.1 Setting up software trigger mode Figure 11-32. Setting up Software Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input.

  • Page 540: Setting Up Hardware Trigger No-Wait Mode

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.7.2 Setting up hardware trigger no-wait mode Figure 11-33. Setting up Hardware Trigger No-Wait Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.

  • Page 541: Setting Up Hardware Trigger Wait Mode

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.7.3 Setting up hardware trigger wait mode Figure 11-34. Setting up Hardware Trigger Wait Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.

  • Page 542: Setup When Using Temperature Sensor

    RL78/G13 CHAPTER 11 A/D CONVERTER <R> 11.7.4 Setup when using temperature sensor (example for software trigger mode and one-shot conversion mode) Figure 11-35. Setup When Using Temperature Sensor Start of setup The ADCEN bit of the PER0 register is set (1), and supplying the clock PER0 register setting starts.

  • Page 543: Setting Up Test Mode

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.7.5 Setting up test mode Figure 11-36. Setting up Test Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. • ADM0 register...

  • Page 544: Snooze Mode Function

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.8 SNOOZE Mode Function In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D conversion is stopped while in the STOP mode, but, by using the SNOOZE mode, A/D conversion can be performed without operating the CPU by inputting a hardware trigger.
  • Page 545 RL78/G13 CHAPTER 11 A/D CONVERTER (1) If an interrupt is generated after A/D conversion ends <R> If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is generated.
  • Page 546 RL78/G13 CHAPTER 11 A/D CONVERTER (2) If no interrupt is generated after A/D conversion ends If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is not generated.

  • Page 547: How To Read A/D Converter Characteristics Table

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.9 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
  • Page 548 RL78/G13 CHAPTER 11 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.

  • Page 549: Cautions For A/D Converter

    RL78/G13 CHAPTER 11 A/D CONVERTER 11.10 Cautions for A/D Converter (1) Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time.
  • Page 550 RL78/G13 CHAPTER 11 A/D CONVERTER Figure 11-46. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AV REFP or equal to or lower than AV and V may enter, clamp with REFM a diode with a small V value (0.3 V or lower).
  • Page 551 RL78/G13 CHAPTER 11 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the pre-change analog input may be set just before the ADS register rewrite.
  • Page 552 RL78/G13 CHAPTER 11 A/D CONVERTER (10) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 11-47. Internal Equivalent Circuit of ANIn Pin ANIn <R> Table 11-6. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) ANIn Pins R1 [kΩ]...

  • Page 553: Chapter 12 Serial Array Unit

    Serial array unit 0 has four serial channels, and serial array unit 1 has two. Each channel can achieve 3-wire serial (CSI), UART, and simplified I C communication. Function assignment of each channel supported by the RL78/G13 is as shown below. • 20, 24, 25-pin products Unit...
  • Page 554 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT • 64-pin products Used as Simplified I Unit Channel Used as CSI Used as UART CSI00 UART0 IIC00 CSI01 IIC01 CSI10 UART1 IIC10 CSI11 IIC11 CSI20 UART2 (supporting LIN-bus) IIC20 CSI21 IIC21 • 80, 100, 128-pin products...

  • Page 555: Functions Of Serial Array Unit

    CHAPTER 12 SERIAL ARRAY UNIT 12.1 Functions of Serial Array Unit Each serial interface supported by the RL78/G13 has the following features. 12.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel.

  • Page 556: Uart (Uart0 To Uart3)

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.1.2 UART (UART0 to UART3) This is a start-stop synchronization function using two lines: serial data transmission (T D) and serial data reception D) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.

  • Page 557: Simplified I 2 C (Iic00, Iic01, Iic10, Iic11, Iic20, Iic21, Iic30, Iic31)

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.1.3 Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master.

  • Page 558: Configuration Of Serial Array Unit

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.2 Configuration of Serial Array Unit The serial array unit includes the following hardware. Table 12-1. Configuration of Serial Array Unit Item Configuration Note 1 Shift register 8 bits or 9 bits Notes 1, 2...
  • Page 559 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Notes 1. The number of bits used as the shift register and buffer register differs depending on the unit and channel. <R> • 20 to 64-pin products and mn = 00, 01: lower 9 bits •...
  • Page 560 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-1 shows the block diagram of the serial array unit 0. Figure 12-1. Block Diagram of Serial Array Unit 0 Noise filter enable Serial output register 0 (SO0) register 0 (NFEN0) SNFEN SNFEN...
  • Page 561 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-2 shows the block diagram of the serial array unit 1. Figure 12-2. Block Diagram of Serial Array Unit 1 <R> Noise filter enable Serial output register 1 (SO1) register 0 (NFEN0) SNFEN...
  • Page 562 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Shift register This is a 9-bit register that converts parallel data into serial data or vice versa. Note 1 In case of the UART communication of nine bits of data, nine bits (bits 0 to 8) are used During reception, it converts data input to the serial pin into parallel data.
  • Page 563 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-3. Format of Serial Data Register mn (SDRmn) (mn = 00, 01, 10, 11) Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H Note Note FFF48H, FFF49H (SDR10) , FFF4AH, FFF4BH (SDR11)

  • Page 564: Registers Controlling Serial Array Unit

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.3 Registers Controlling Serial Array Unit Serial array unit is controlled by the following registers. • Peripheral enable register 0 (PER0) • Serial clock select register m (SPSm) • Serial mode register mn (SMRmn) •...
  • Page 565 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Peripheral enable register 0 (PER0) PER0 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
  • Page 566 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Serial clock select register m (SPSm) The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register , and CKm0 is selected by bits 3 to 0.
  • Page 567 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-6. Format of Serial Clock Select Register m (SPSm) Address: F0126H, F0127H (SPS0), F0166H, F0167H (SPS1) After reset: 0000H Symbol SPSm Note 1 Section of operation clock (CKmk) = 2 MHz = 5 MHz...
  • Page 568 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Serial mode register mn (SMRmn) The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation clock (f ), specify whether the serial clock (f...
  • Page 569 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-7. Format of Serial Mode Register mn (SMRmn) (2/2) Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), After reset: 0020H F0150H, F0151H (SMR10) to F0156H, F0157H (SMR13) Symbol SMRmn Note Note Controls inversion of level of receive data of channel n in UART mode Falling edge is detected as the start bit.
  • Page 570 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2) Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), After reset: 0087H F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13) Symbol SLCm DLSm SCRmn...
  • Page 571 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/2) Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), After reset: 0087H F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13) Symbol SCRmn SLCm DLSm...
  • Page 572 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (5) Higher 7 bits of the serial data register mn (SDRmn) <R> The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) of SDR00,...
  • Page 573 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Cautions 1. Be sure to clear bit 8 of the SDR02, SDR03, SDR12, SDR13, and SDR10, and SDR11 of 20 to 64- pin products to “0”. 2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
  • Page 574 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (6) Serial flag clear trigger register mn (SIRmn) The SIRmn register is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of serial status register mn is cleared to 0.
  • Page 575 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (7) Serial status register mn (SSRmn) The SSRmn register is a register that indicates the communication status and error occurrence status of channel n. The errors indicated by this register are a framing error, parity error, and overrun error.
  • Page 576 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-11. Format of Serial Status Register mn (SSRmn) (2/2) Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03), After reset: 0000H F0140H, F0141H (SSR10) to F0146H, F0147H (SSR13) Symbol SSRmn FEFm Note FEFm Framing error detection flag of channel n Note No error occurs.
  • Page 577 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (8) Serial channel start register m (SSm) The SSm register is a trigger register that is used to enable starting communication/count by each channel. When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1 (Operation is enabled).
  • Page 578 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (9) Serial channel stop register m (STm) The STm register is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0 (operation is stopped).
  • Page 579 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (10) Serial channel enable status register m (SEm) The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1.
  • Page 580 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (11) Serial output enable register m (SOEm) The SOEm register is a register that is used to enable or stop output of the serial communication operation of each channel. Channel n that enables serial output cannot rewrite by software the value of the SOmn bit of serial output register m (SOm) to be described below, and a value reflected by a communication operation is output from the serial data output pin.
  • Page 581 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (12) Serial output register m (SOm) The SOm register is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n.
  • Page 582 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (13) Serial output level register m (SOLm) The SOLm register is a register that is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0 for corresponding bit in the CSI mode and <R>...
  • Page 583 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (14) Serial standby control register m (SSCm) The SSC0 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when receiving CSI00 or UART0 serial data. Note...
  • Page 584 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (15) Input switch control register (ISC) The ISC1 and ISC0 bits of the ISC register are used to realize a LIN-bus communication operation by UART2 in coordination with an external interrupt and the timer array unit.
  • Page 585 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (16) Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel.
  • Page 586 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (17) Port input mode registers 0, 1, 4, 5, 8, 14 (PIM0, PIM1, PIM4, PIM5, PIM8, PIM14) These registers set the input buffer of ports 0, 1, 4, 5, 8, and 14 in 1-bit units.
  • Page 587 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (18) Port output mode registers 0, 1, 4, 5, 7 to 9, 14 (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) These registers set the output mode of ports 0, 1, 4, 5, 7 to 9, and 14 in 1-bit units.
  • Page 588 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (19) Port mode registers 0, 1, 3 to 5, 7 to 9, and 14 (PM0, PM1, PM3 to PM5, PM7 to PM9, and PM14) These registers set input/output of ports 0, 1, 3 to 5, 7 to 9, and 14 in 1-bit units.
  • Page 589 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-23. Format of Port Mode Registers 0, 1, 3 to 5, 7 to 9, and 14 (PM0, PM1, PM3 to PM5, PM7 to PM9, and 14) Address: FFF20H After reset: FFH Symbol PM06...

  • Page 590: Operation Stop Mode

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.4 Operation stop mode Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pin for serial interface can be used as port function pins in this mode.

  • Page 591: Stopping The Operation By Units

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.4.1 Stopping the operation by units The stopping of the operation by units is set by using peripheral enable register 0 (PER0). The PER0 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.

  • Page 592: Stopping The Operation By Channels

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 12-25. Each Register Setting When Stopping the Operation by Channels (a) Serial channel stop register m (STm) … This register is a trigger register that is used to enable stopping communication/count by each channel.

  • Page 593: Operation Of 3-Wire Serial I/O (Csi00, Csi01, Csi10, Csi11, Csi20, Csi21, Csi30, Csi31) Communication

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) Communication This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines.
  • Page 594 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT The channels supporting 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) are channels 0 to 3 of SAU0 and channels 0 to 3 of SAU1. • 20, 24, 25-pin products Used as Simplified I...
  • Page 595 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT • 64-pin products Used as Simplified I Unit Channel Used as CSI Used as UART CSI00 UART0 IIC00 CSI01 IIC01 CSI10 UART1 IIC10 CSI11 IIC11 CSI20 UART2 (supporting LIN-bus) IIC20 CSI21 IIC21 • 80, 100, 128-pin products...

  • Page 596: Master Transmission

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.1 Master transmission Master transmission is that the RL78/G13 outputs a transfer clock and transmits data to another device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31 Target channel Channel Channel...
  • Page 597 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-26. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn...
  • Page 598 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-26. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
  • Page 599 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-27. Initial Setting Procedure for Master Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
  • Page 600 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-28. Procedure for Stopping Master Transmission Starting setting to stop If there is any data being transferred, wait for their completion. TSFmn = 0? Write 1 to the STmn bit of the target Setting the STm register channel.
  • Page 601 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-29. Procedure for Resuming Master Transmission Starting setting for resumption Disable data output and clock output of Port manipulation (Essential) the target channel by setting a port register and a port mode register.
  • Page 602 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-30. Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2...
  • Page 603 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-31. Flowchart of Master Transmission (in Single-Transmission Mode) <R> Starting CSI communication For the initial setting, refer to Figure 12-27. SAU default setting (Select Transfer end interrupt) Set data for transmission and the number of data. Clear communication end flag...
  • Page 604 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-32. Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2...
  • Page 605 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-33. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, refer to Figure 12-27. <1> SAU default setting (Select buffer empty interrupt) Set data for transmission and the number of data. Clear communication end flag...

  • Page 606: Master Reception

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.2 Master reception Master reception is that the RL78/G13 outputs a transfer clock and receives data from other device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31 Target channel Channel Channel...
  • Page 607 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-34. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn...
  • Page 608 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-34. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (2/2) (e) Serial output enable register m (SOEm) …The register that not used in this mode.
  • Page 609 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-35. Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
  • Page 610 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-37. Procedure for Resuming Master Reception Starting setting for resumption Disable clock output of the target channel by setting a port register and a Port manipulation (Essential) port mode register. Re-set the register to change the operation...
  • Page 611 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 12-38. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 Receive data 1 Receive data 2...
  • Page 612 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-39. Flowchart of Master Reception (in Single-Reception Mode) <R> Starting CSI communication For the initial setting, refer to Figure 12-35. SAU default setting (Select Transfer end interrupt) Setting storage area of the receive data, number of communication data...
  • Page 613 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous reception mode) Figure 12-40. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Dummy data...
  • Page 614 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-41. Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication For the initial setting, refer to Figure 12-35. buffer empty (Select interrupt) SAU default setting <1> Setting storage area of the receive data, number of communication data...

  • Page 615: Master Transmission/Reception

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.3 Master transmission/reception Master transmission/reception is that the RL78/G13 outputs a transfer clock and transmits/receives data to/from other device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31 Target channel Channel Channel...
  • Page 616 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-42. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn...
  • Page 617 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-42. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
  • Page 618 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-43. Initial Setting Procedure for Master Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 619 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-45. Procedure for Resuming Master Transmission/Reception Starting setting for resumption Disable data output and clock output of the target channel by setting a port Port manipulation (Essential) register and a port mode register.
  • Page 620 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 12-46. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 3 Receive data 2...
  • Page 621 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-47. Flowchart of Master Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication For the initial setting, refer to Figure 12-43. SAU default setting (Select transfer end interrupt) Setting storage data and number of data for transmission/reception data...
  • Page 622 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-48. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Transmit data 2...
  • Page 623 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-49. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) <R> Starting setting For the initial setting, refer to Figure 12-43. <1> SAU default setting (Select buffer empty interrupt) Setting storage data and number of data for transmission/reception data...

  • Page 624: Slave Transmission

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.4 Slave transmission Slave transmission is that the RL78/G13 transmits data to another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11 CSI20...
  • Page 625 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-50. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn...
  • Page 626 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-50. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
  • Page 627 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-51. Initial Setting Procedure for Slave Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 628 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-53. Procedure for Resuming Slave Transmission Starting setting for resumption Stop the target for communication or wait Manipulating target for communication (Essential) until the target completes its operation. Disable data output of the target channel...
  • Page 629 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-54. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 2 Transmit data 1...
  • Page 630 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-55. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication For the initial setting, refer to Figure 12-51. SAU default setting (Select transfer end interrupt) Set storage area and the number of data for transmit data...
  • Page 631 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-56. Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 3...
  • Page 632 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-57. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, refer to Figure 12-51. <1> SAU default setting (Select buffer empty interrupt) Setting transmit data Set storage area and the number of data for transmit data...

  • Page 633: Slave Reception

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.5 Slave reception Slave reception is that the RL78/G13 receives data from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11 CSI20...
  • Page 634 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-58. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn...
  • Page 635 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-58. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) (2/2) (e) Serial output enable register m (SOEm) …The Register that not used in this mode.
  • Page 636 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-59. Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 637 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-61. Procedure for Resuming Slave Reception Starting setting for resumption Stop the target for communication or wait (Essential) Manipulating target for communication until the target completes its operation. Disable clock output of the target...
  • Page 638 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 12-62. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Receive data 1...
  • Page 639 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-63. Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication For the initial setting, refer to Figure 12-59. SAU default setting (Select transfer end interrupt only) Clear storage area setting and the number of receive data...

  • Page 640: Slave Transmission/Reception

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.6 Slave transmission/reception Slave transmission/reception is that the RL78/G13 transmits/receives data to/from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11 CSI20...
  • Page 641 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-64. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn...
  • Page 642 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-64. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
  • Page 643 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-65. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
  • Page 644 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-66. Procedure for Stopping Slave Transmission/Reception Starting setting to stop Write 1 to the STmn bit of the target Setting the STm register channel. Set the SOEmn bit to 0 and stop the Changing setting of the SOEm register output of the target channel.
  • Page 645 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-67. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Stop the target for communication or wait (Essential) Manipulating target for communication until the target completes its operation. Disable data output of the target channel...
  • Page 646 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 12-68. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2 Receive data 3...
  • Page 647 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-69. Flowchart of Slave Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication For the initial setting, refer to Figure 12-65 SAU default setting (Select Transfer end interrupt) Setting storage area and number of data for transmission/reception data...
  • Page 648 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-70. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Transmit data 2...
  • Page 649 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-71. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, refer to Figure 12-59 <1> SAU default setting (Select buffer empty interrupt) Setting storage area and number of data for transmission/reception data...

  • Page 650: Snooze Mode Function

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.7 SNOOZE mode function When SCKp pin input is detected while in the STOP mode, the SNOOZE mode makes data reception that does not require the CPU possible. Only following CSIs can be specified for asynchronous reception.
  • Page 651 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-73. Flowchart of SNOOZE Mode Operation (once startup) Starting setting TSFmn = 0 for all channels? Become the operation STOP status (SEm0 = 0) <1> Write STm0 bit to 1 SMRm0, SCRm0 : Communication setting...
  • Page 652 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) SNOOZE mode operation (continuous startup) Figure 12-74. Timing Chart of SNOOZE Mode Operation (continuous startup) (Type 1: DAPmn = 0, CKPmn = 0) CPU operation status Normal peration STOP mode SNOOZE mode Normal peration...
  • Page 653 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-75. Flowchart of SNOOZE Mode Operation (continuous startup) Starting setting TSFmn = 0 for all channels? Become the operation STOP status (SEm0 = 0) Write STm0 bit to 1 <1> SMRm0, SCRm0 : Communication setting...

  • Page 654: Calculating Transfer Clock Frequency

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.8 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) communication can be calculated by the following expressions. (1) Master ) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz]...
  • Page 655 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Table 12-2. Selection of Operation Clock For 3-Wire Serial I/O Note SMRmn SPSm Register Operation Clock (f Register CKSmn = 32 MHz 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz...

  • Page 656: Procedure For Processing Errors That Occurred During 3-Wire Serial I/O

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) communication The procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) communication is described in Figure 12-76.

  • Page 657: Operation Of Uart (Uart0 To Uart3) Communication

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.6 Operation of UART (UART0 to UART3) Communication This is a start-stop synchronization function using two lines: serial data transmission (T D) and serial data reception D) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
  • Page 658 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT UART0 uses channels 0 and 1 of SAU0. UART1 uses channels 2 and 3 of SAU0. UART2 uses channels 0 and 1 of SAU1. UART3 uses channels 2 and 3 of SAU1. • 20, 24, and 25-pin products...
  • Page 659 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT • 64-pin products Used as Simplified I Unit Channel Used as CSI Used as UART CSI00 UART0 IIC00 CSI01 IIC01 CSI10 UART1 IIC10 CSI11 IIC11 CSI20 UART2 (supporting LIN- IIC20 bus) CSI21 IIC21 • 80, 100, 128-pin products...

  • Page 660: Uart Transmission

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.6.1 UART transmission UART transmission is an operation to transmit data from the RL78/G13 to another device asynchronously (start-stop synchronization). Of two channels used for UART, the even channel is used for UART transmission.
  • Page 661 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-77. Example of Contents of Registers for UART Transmission of UART (UART0 to UART3) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn MDmn2 MDmn1 MDmn0 Operation clock (f...
  • Page 662 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-77. Example of Contents of Registers for UART Transmission of UART (UART0 to UART3) (2/2) (e) Serial output register m (SOm) … Sets only the bits of the target channel. CKOm3 CKOm2 CKOm1...
  • Page 663 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-78. Initial Setting Procedure for UART Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 664 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-79. Procedure for Stopping UART Transmission Starting setting to stop Write 1 to the STmn bit of the target Setting the STm register channel. Set the SOEmn bit to 0 and stop the Setting the SOEm register output.
  • Page 665 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-80. Procedure for Resuming UART Transmission Starting setting for resumption Disable data output of the target channel (Essential) Port manipulation by setting a port register and a port mode register. Re-set the register to change the...
  • Page 666 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-81. Timing Chart of UART Transmission (in Single-Transmission Mode) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 TxDq pin Transmit data 1...
  • Page 667 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-82. Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication Setting the SAUmEN bit of the PER0 register to 1 Setting operation clock by the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while the...
  • Page 668 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-83. Timing Chart of UART Transmission (in Continuous Transmission Mode) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 3 Transmit data 2 TxDq pin Transmit data 3...
  • Page 669 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-84. Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication Setting the SAUmEN bit of the PER0 register to 1 Setting operation clock by the SPSm register Specify the initial settings while the...

  • Page 670: Uart Reception

    CHAPTER 12 SERIAL ARRAY UNIT 12.6.2 UART reception UART reception is an operation wherein the RL78/G13 asynchronously receives data from another device (start-stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set.
  • Page 671 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-85. Example of Contents of Registers for UART Reception of UART (UART0 to UART3) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f...
  • Page 672 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-85. Example of Contents of Registers for UART Reception of UART (UART0 to UART3) (2/2) (e) Serial output register m (SOm) … The register that not used in this mode. CKOm3 CKOm2 CKOm1...
  • Page 673 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-86. Initial Setting Procedure for UART Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 674 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-88. Procedure for Resuming UART Reception Starting setting for resumption Stop the target for communication or wait until the target completes its operation. (Essential) Manipulating target for communication Re-set the register to change the operation...
  • Page 675 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow Figure 12-89. Timing Chart of UART Reception SSmn STmn SEmn Receive data 3 SDRmn Receive data 2 Receive data 1 RxDq pin Receive data 1 Receive data 2 Receive data 3...
  • Page 676 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-90. Flowchart of UART Reception Starting UART communication Setting the SAUmEN bit of the PER0 register to 1 Setting transfer rate by the SPSm register Specify the initial settings SMRmn, SMRmr, SCRmn: Setting communication...

  • Page 677: Snooze Mode Function

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.6.3 SNOOZE mode function When RxDq pin input is detected while in the STOP mode, the SNOOZE mode makes data reception that does not require the CPU possible. Only following UARTs can be specified for the reception baud rate adjustment function.
  • Page 678 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) SNOOZE mode operation (Abnormal Operation <1>) Abnormal operation <1> is the operation performed when a communication error occurs while SSECm = 0. Because SSECm = 0, an error interrupt (INTSREq) is generated when a communication error occurs.
  • Page 679 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-93. Flowchart of SNOOZE Mode Operation (Normal Operation/Abnormal Operation <1>) Setting start Does TSFmn = 0 on all channels? The operation of channels 0 and 1 of unit 0 stop. Writing 1 to the STmn bit <1>...
  • Page 680 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) SNOOZE mode operation (Abnormal Operation <2>) Abnormal operation <2> is the operation performed when a communication error occurs while SSECm = 1. Because SSECm = 1, an error interrupt (INTSREq) is not generated when a communication error occurs.
  • Page 681 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-95. Flowchart of SNOOZE Mode Operation (Abnormal Operation <2>) Setting start Does TSFmn = 0 on all channels? Clear the all error flags SIRm1 = 00H The operation of channels 0 and 1 of unit m stop.

  • Page 682: Calculating Baud Rate

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.6.4 Calculating baud rate (1) Baud rate calculation expression The baud rate for UART (UART0 to UART3) communication can be calculated by the following expressions. (Baud rate) = {Operation clock (f ) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [bps] Caution Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B, 0000001B) is prohibited.
  • Page 683 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Table 12-3. Selection of Operation Clock For UART Note SMRmn SPSm Register Operation Clock (f Register CKSmn = 32 MHz 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz...
  • Page 684 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Baud rate error during transmission The baud rate error of UART (UART0 to UART3) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
  • Page 685 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UART0 to UART3) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.

  • Page 686: Procedure For Processing Errors That Occurred During Uart (Uart0 To Uart3) Communication667

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.6.5 Procedure for processing errors that occurred during UART (UART0 to UART3) communication The procedure for processing errors that occurred during UART (UART0 to UART3) communication is described in Figures 12-97 and 12-98. Figure 12-97. Processing Procedure in Case of Parity Error or Overrun Error...

  • Page 687: Lin Communication Operation

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.7 LIN Communication Operation 12.7.1 LIN transmission Of UART transmission, UART2 of the 30, 32, 36, 40, 44, 48, 52, 64, 80, 100, and 128-pin products support LIN communication. For LIN transmission, channel 0 of unit 1 is used.
  • Page 688 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol designed to reduce the cost of an automobile network. Communication of LIN is single-master communication and up to 15 slaves can be connected to one master.
  • Page 689 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-100. Flowchart for LIN Transmission Starting LIN communication Setting baud rate Transition to the state in which Writing 1 to the SS10 bit communication is enabled Setting transfer data 00H Transmitting wakeup signal frame...

  • Page 690: Lin Reception

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.7.2 LIN reception Of UART reception, UART2 of the 30, 32, 36, 40, 44, 48, 52, 64, 80, 100, and 128-pin products support LIN communication. For LIN reception, channel 1 of unit 1 is used.
  • Page 691 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-101. Reception Operation of LIN Wakeup signal Sync break Sync field Identification Data filed Data filed Checksum frame field field field LIN Bus 13-bit SBF Data Data Data reception reception reception reception reception reception <5>...
  • Page 692 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-102 and figure 12-103 show the configuration of a port that manipulates reception of LIN. The wakeup signal transmitted from the master of LIN is received by detecting an edge of an external interrupt (INTP0).
  • Page 693 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-103 Port Configuration for Manipulating Reception of LIN (44, 48, 52, 64-pin) Selector P14/RxD2/SI20/SDA20 RXD2 input Port mode (PM14) Output latch (P14) Selector P137/INTP0 INTP0 input Port input switch control (ISC0) <ISC0> 0: Selects INTP0 (P137)
  • Page 694 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT The peripheral functions used for the LIN communication operation are as follows. <Peripheral functions used> • External interrupt (INTP0); Wakeup signal detection Usage: To detect an edge of the wakeup signal and the start of communication •...
  • Page 695 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-104. Flowchart of LIN Reception Starting LIN communication Setting TAU in capture mode (to measure low-level width) Detecting low-level width Wakeup signal frame Wakeup detected? Detecting low-level width Sync break field SBF detected?

  • Page 696: Operation Of Simplified I C (Iic00, Iic01, Iic10, Iic11, Iic20, Iic21, Iic30, Iic31) Communication

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.8 Operation of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) Communication This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA).
  • Page 697 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT The channel supporting simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) is channels 0 to 3 of SAU0 and channel 0 and 1 of SAU1. • 20, 24, 25-pin products Used as Simplified I...
  • Page 698 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT • 64-pin products Used as Simplified I Unit Channel Used as CSI Used as UART CSI00 UART0 IIC00 CSI01 IIC01 CSI10 UART1 IIC10 CSI11 IIC11 CSI20 UART2 (supporting LIN-bus) IIC20 CSI21 IIC21 • 80, 100, 128-pin products...

  • Page 699: Address Field Transmission

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.8.1 Address field transmission Address field transmission is a transmission operation that first executes in I C communication to identify the target for transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in one frame.
  • Page 700 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-105. Example of Contents of Registers for Address Field Transmission of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) (1/2) (a) Serial mode register mn (SMRmn) SMRmn...
  • Page 701 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-105. Example of Contents of Registers for Address Field Transmission of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) (2/2) (f) Serial channel start register m (SSm) … Sets only the bits of the target channel is 1.
  • Page 702 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-106. Initial Setting Procedure for Address Field Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 703 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow Figure 12-107. Timing Chart of Address Field Transmission SSmn SEmn SOEmn SDRmn Address field transmission SCLr output CKOmn bit manipulation SDAr output SOmn bit manipulation Address SDAr input Shift Shift operation...
  • Page 704 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-108. Flowchart of Address Field Transmission Starting IIC communication SMRmn, SCRmn: Setting communication SPSm, SDRmn[15:9]: Setting transfer rate Specify the initial settings Writing 0 to the SOmn bit while the SEmn bit of...

  • Page 705: Data Transmission

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.8.2 Data transmission Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field. After all data are transmitted to the slave, a stop condition is generated and the bus is released.
  • Page 706 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-109. Example of Contents of Registers for Data Transmission of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) (1/2) (a) Serial mode register mn (SMRmn) … Do not manipulate this register during data transmission/reception.
  • Page 707 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-109. Example of Contents of Registers for Data Transmission of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) (2/2) (f) Serial channel start register m (SSm) … Do not manipulate this register during data transmission/reception.
  • Page 708 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Processing flow Figure 12-110. Timing Chart of Data Transmission SSmn “L” SEmn “H” SOEmn “H” SDRmn Transmit data 1 SCLr output SDAr output SDAr input Shift Shift operation register mn INTIICr TSFmn Figure 12-111. Flowchart of Data Transmission...

  • Page 709: Data Reception

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.8.3 Data reception Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field. After all data are received to the slave, a stop condition is generated and the bus is released.
  • Page 710 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-112. Example of Contents of Registers for Data Reception of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) (1/2) (a) Serial mode register mn (SMRmn) … Do not manipulate this register during data transmission/reception.
  • Page 711 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-112. Example of Contents of Registers for Data Reception of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) (2/2) (f) Serial channel start register m (SSm) … Do not manipulate this register during data transmission/reception.
  • Page 712 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Processing flow Figure 12-113. Timing Chart of Data Reception (a) When starting data reception SSmn STmn SEmn SOEmn “H” TXEmn, TXEmn = 1 / RXEmn = 0 TXEmn = 0 / RXEmn = 1...
  • Page 713 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-114. Flowchart of Data Reception Address field transmission completed Writing 1 to the STmn bit Writing 0 to the TXEmn bit, and 1 to the RXEmn bit Writing 1 to the SSmn bit...

  • Page 714: Stop Condition Generation

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.8.4 Stop condition generation After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released. (1) Processing flow Figure 12-115. Timing Chart of Stop Condition Generation...

  • Page 715: Calculating Transfer Rate

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.8.5 Calculating transfer rate The transfer rate for simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) communication can be calculated by the following expressions. (Transfer rate) = {Operation clock (f ) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 Caution Setting SDRmn[15:9] = 0000000B is prohibited.
  • Page 716 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Table 12-4. Selection of Operation Clock For Simplified I Note SMRmn SPSm Register Operation Clock (f Register CKSmn = 32 MHz 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz...

  • Page 717: Procedure For Processing Errors That Occurred During Simplified I C

    RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.8.6 Procedure for processing errors that occurred during simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) communication The procedure for processing errors that occurred during simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) communication is described in Figure 12-117 and 12-118.

  • Page 718: Chapter 13 Serial Interface Iica

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA CHAPTER 13 SERIAL INTERFACE IICA The number of channels of the serial Interface IICA differs, depending on the product. 20-pin 24, 25, 30, 32, 36, 40, 80, 100, 128-pin 44, 48, 52, 56, 64-pin −...
  • Page 719 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-1. Block Diagram of Serial Interface IICA Internal bus IICA status register 0 (IICS0) WUP0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IICA control register 00 (IICCTL00) Sub-circuit for standby IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0...
  • Page 720 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-2 shows a serial bus configuration example. Figure 13-2. Serial Bus Configuration Example Using I C Bus Serial data bus Master CPU1 Master CPU2 SDAA0 SDAA0 Slave CPU1 Slave CPU2 Serial clock SCLA0...

  • Page 721: Configuration Of Serial Interface Iica

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table 13-1. Configuration of Serial Interface IICA Item Configuration Registers IICA shift register 0 (IICA0) Slave address register 0 (SVA0) Control registers...
  • Page 722 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-4. Format of Slave Address Register 0 (SVA0) Address: F0234H After reset: 00H Symbol Note SVA0 Note Bit 0 is fixed to 0. (3) SO latch The SO latch is used to retain the SDAA0 pin’s output level.
  • Page 723 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (13) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the STCEN bit.

  • Page 724: Registers Controlling Serial Interface Iica

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.3 Registers Controlling Serial Interface IICA Serial interface IICA is controlled by the following eight registers. • Peripheral enable register 0 (PER0) • IICA control register 00 (IICCTL00) • IICA flag register 0 (IICF0) •...
  • Page 725 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (2) IICA control register 00 (IICCTL00) This register is used to enable/stop I C operations, set wait timing, and set other I C operations. The IICCTL00 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0, WTIM0, and ACKE0 bits while IICE0 = 0 or during the wait period.
  • Page 726 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (1/4) Address: F0230H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICCTL00 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 IICE0...
  • Page 727 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (2/4) Note 1 SPIE0 Enable/disable generation of interrupt request when stop condition is detected Disable Enable If the WUP0 bit of IICA control register 01 (IICCTL01) is 1, no stop condition interrupt will be generated even if SPIE0 = 1.
  • Page 728 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (3/4) Note STT0 Start condition trigger Do not generate a start condition. When bus is released (in standby state, when IICBSY = 0): If this bit is set (1), a start condition is generated (startup as the master).
  • Page 729 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (4/4) SPT0 Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). Cautions concerning set timing • For master reception: Cannot be set to 1 during transfer.
  • Page 730 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (3) IICA status register 0 (IICS0) This register indicates the status of I The IICS0 register is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait period.
  • Page 731 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-7. Format of IICA Status Register 0 (IICS0) (2/3) EXC0 Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXC0 = 0) Condition for setting (EXC0 = 1) •...
  • Page 732 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-7. Format of IICA Status Register 0 (IICS0) (3/3) ACKD0 Detection of acknowledge (ACK) Acknowledge was not detected. Acknowledge was detected. Condition for clearing (ACKD0 = 0) Condition for setting (ACKD0 = 1) •...
  • Page 733 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-8. Format of IICA Flag Register 0 (IICF0) Note Address: FFF52H After reset: 00H <7> <6> <1> <0> Symbol IICF0 STCF0 IICBSY0 STCEN0 IICRSV0 STCF0 STT0 clear flag Generate start condition Start condition generation unsuccessful: clear the STT0 flag...
  • Page 734 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (5) IICA control register 01 (IICCTL01) This register is used to set the operation mode of I C and detect the statuses of the SCLA0 and SDAA0 pins. The IICCTL01 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-only.
  • Page 735 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-9. Format of IICA Control Register 01 (IICCTL01) (2/2) CLD0 Detection of SCLA0 pin level (valid only when IICE0 = 1) The SCLA0 pin was detected at low level. The SCLA0 pin was detected at high level.
  • Page 736 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (6) IICA low-level width setting register 0 (IICWL0) This register is used to set the low-level width (t ) and data hold time (t ) of the SCLA0 pin signal that is HD:DAT output by serial interface IICA. The data hold time is decided by value the higher 6 bits of IICWL register.
  • Page 737 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (8) Port mode register 6 (PM6) This register sets the input/output of port 6 in 1-bit units. When using the P60/SCLA0 pin as clock I/O and the P61/SDAA0 pin as serial data I/O, clear PM60 and PM61, and the output latches of P60 and P61 to 0.

  • Page 738: I C Bus Mode Functions

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.4 I C Bus Mode Functions 13.4.1 Pin configuration The serial clock pin (SCLA0) and the serial data bus pin (SDAA0) are configured as follows. (1) SCLA0 ..This pin is used for serial clock input and output.

  • Page 739: Setting Transfer Clock By Using Iicwl0 And Iicwh0 Registers

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers (1) Setting transfer clock on master side Transfer clock = IICWL0 + IICWH0 + f At this time, the optimal setting values of the IICWL0 and IICWH0 registers are as follows.
  • Page 740 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Caution Note the minimum f operation frequency when setting the transfer clock. The minimum f operation frequency for serial interface IICA is determined according to the mode. Fast mode: = 3.5 MHz (MIN.) Fast mode plus: f = 10 MHz (MIN.)

  • Page 741: I C Bus Definitions And Control Methods

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I C bus. Figure 13-14 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I bus’s serial data bus.

  • Page 742: Addresses

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.

  • Page 743: Acknowledge (Ack)

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued.

  • Page 744: Stop Condition

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.5 Stop condition When the SCLA0 pin is at high level, changing the SDAA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed.

  • Page 745: Wait

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLA0 pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin.
  • Page 746 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-20. Wait (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKE0 = 1) Master Master and slave both wait after output of ninth clock...

  • Page 747: Canceling Wait

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.7 Canceling wait The I C usually cancels a wait state by the following processing. • Writing data to the IICA shift register 0 (IICA0) • Setting bit 5 (WREL0) of IICA control register 00 (IICCTL00) (canceling wait) •...

  • Page 748: Interrupt Request (Intiica0) Generation Timing And Wait Control

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.8 Interrupt request (INTIICA0) generation timing and wait control The setting of bit 3 (WTIM0) of IICA control register 00 (IICCTL00) determines the timing by which INTIICA0 is generated and the corresponding wait control, as shown in Table 13-2.

  • Page 749: Address Match Detection Method

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.9 Address match detection method In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An interrupt request (INTIICA0) occurs when the address set to the slave address register 0 (SVA0) matches the slave address sent by the master device, or when an extension code has been received.

  • Page 750: Arbitration

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.12 Arbitration When several master devices simultaneously generate a start condition (when the STT0 bit is set to 1 before the STD0 bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs.
  • Page 751 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Table 13-4. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 During address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission...

  • Page 752: Wakeup Function

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.13 Wakeup function The I C bus slave function is a function that generates an interrupt request signal (INTIICA0) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIICA0 signal from occurring when addresses do not match.
  • Page 753 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-23. Flow When Setting WUP0 = 0 upon Address Match (Including Extension Code Reception) STOP mode state INTIICA0 = 1? WUP0 = 0 Wait Waits for 5 clocks. Reading IICS0 Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA.
  • Page 754 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-24. When Operating as Master Device after Releasing STOP Mode other than by INTIICA0 START SPIE0 = 1 WUP0 = 1 STOP instruction STOP mode state Releasing STOP mode Releases STOP mode by an interrupt other than INTIICA0.

  • Page 755: Communication Reservation

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.14 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSV) of IICA flag register 0 (IICF0) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released.
  • Page 756 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-25 shows the communication reservation timing. Figure 13-25. Communication Reservation Timing Write to Program processing STT0 = 1 IICA0 Communi- Set SPD0 cation Hardware processing STD0 reservation INTIICA0 SCLA0 SDAA0 Generate by master device with bus mastership...
  • Page 757 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-27. Communication Reservation Protocol SET1 STT0 Sets STT0 flag (communication reservation) Defines that communication reservation is in effect Define communication (defines and sets user flag to any part of RAM) reservation Note 1 Secures wait time by software.
  • Page 758 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (2) When communication reservation function is disabled (bit 0 (IICRSV) of IICA flag register 0 (IICF0) = 1) When bit 1 (STT0) of IICA control register 00 (IICCTL00) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated.

  • Page 759: Cautions

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.15 Cautions (1) When STCEN = 0 Immediately after I C operation is enabled (IICE0 = 1), the bus communication status (IICBSY = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication.

  • Page 760: Communication Operations

    This flowchart is broadly divided into the initial settings, communication waiting, and communication processing. The processing when the RL78/G13 looses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. Execute the initial settings at startup to take part in a communication. Then, wait for the communication request as the master or wait for the specification as the slave.
  • Page 761 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (1) Master operation in single-master system Figure 13-28. Master Operation in Single-Master System START Note Initializing I C bus Setting of the port used alternatively as the pin to be used. Setting port First, set the port to input mode and the output latch to 0 (see 13.3 (8) Port mode register 6 (PM6)).
  • Page 762 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (2) Master operation in multi-master system Figure 13-29. Master Operation in Multi-Master System (1/3) START Setting of the port used alternatively as the pin to be used. Setting port First, set the port to input mode and the output latch to 0 (see 13.3 (8) Port mode register 6 (PM6)).
  • Page 763 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-29. Master Operation in Multi-Master System (2/3) Enables reserving communication. Prepares for starting communication STT0 = 1 (generates a start condition). Note Secure wait time by software. Wait MSTS0 = 1? INTIICA0 interrupt occurs? Waits for bus release (communication being reserved).
  • Page 764 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-29. Master Operation in Multi-Master System (3/3) Starts communication Writing IICA0 (specifies an address and transfer direction). INTIICA0 interrupt occurs? Waits for detection of ACK. MSTS0 = 1? ACKD0 = 1? TRC0 = 1?
  • Page 765 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIICA0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary.
  • Page 766 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The main processing of the slave operation is explained next. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt.

  • Page 767: Timing Of I 2 C Interrupt Request (Intiica0) Occurrence

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICA0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIICA0 interrupt checks the status, and the following operations are performed.
  • Page 768 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 1000×110B...
  • Page 769 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 SPT0 = 1 ↓ ↓ AD6 to AD0 R/W ACK D7 to D0...
  • Page 770 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 1010×110B 2: IICS0 = 1010×000B...
  • Page 771 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0001×110B...
  • Page 772 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches with SVA0) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0001×110B...
  • Page 773 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= extension code)) AD6 to AD0 R/W ACK D7 to D0...
  • Page 774 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK...
  • Page 775 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. (a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIM0 = 0...
  • Page 776 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches SVA0) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0010×010B...
  • Page 777 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0010×010B...
  • Page 778 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK...
  • Page 779 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 00000001B Remark : Generated only when SPIE0 = 1...
  • Page 780 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0101×110B 2: IICS0 = 0001×100B 3: IICS0 = 0001××00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×:...
  • Page 781 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0110×010B 2: IICS0 = 0010×110B 3: IICS0 = 0010×100B 4: IICS0 = 0010××00B 5: IICS0 = 00000001B...
  • Page 782 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (b) When arbitration loss occurs during transmission of extension code AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0110×010B Sets LREL0 = 1 by software 2: IICS0 = 00000001B...
  • Page 783 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 10001110B 2: IICS0 = 01000100B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1...
  • Page 784 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (ii) Extension code AD6 to AD0 R/W ACK D7 to Dn AD6 to AD0 D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 01100010B Sets LREL0 = 1 by software 3: IICS0 = 00000001B...
  • Page 785 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 1: IICS0 = 1000×110B...
  • Page 786 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 1: IICS0 = 1000×110B...
  • Page 787 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 1: IICS0 = 1000×110B...

  • Page 788: Timing Charts

    RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.6 Timing Charts When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of the IICA status register 0 (IICS0)), which specifies the data transfer direction, and then starts serial communication with the slave device.
  • Page 789 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4) (1) Start condition ~ address ~ data Master side Note 1 IICA0 <2>...
  • Page 790 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <1> to <6> in (1) Start condition ~ address ~ data in Figure 13-32 are explained below. <1> The start condition trigger is set by the master device (STT0 = 1) and a start condition (i.e. SCLA0 = 1 changes SDAA0 from 1 to 0) is generated once the bus data line goes low (SDAA0).
  • Page 791 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/4) (2) Address ~ data ~ data Master side Note 1 Note 1 IICA0 <5>...
  • Page 792 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <3> to <10> in (2) Address ~ data ~ data in Figure 13-32 are explained below. Note <3> In the slave device if the address received matches the address (SVA0 value) of a slave device , that slave device sends an ACK by hardware to the master device.
  • Page 793 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/4) (3) Data ~ data ~ Stop condition Master side Note 1 IICA0 <9>...
  • Page 794 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <7> to <15> in (3) Data ~ data ~ stop condition in Figure 13-32 are explained below. <7> After data transfer is completed, because of ACKE0 = 1, the slave device sends an ACK by hardware to the master device.
  • Page 795 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4) (4) Data ~ restart condition ~ address Master side IICA0 <iii> ACKD0 (ACK detection)
  • Page 796 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The following describes the operations in Figure 13-32 (4) Data ~ restart condition ~ address. After the operations in steps <7> and <8>, the operations in steps <i> to <iii> are performed. These steps return the processing to step <iii>, the data transmission step.
  • Page 797 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33. Example of Slave to Master Communication (8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) (1) Start condition ~ address ~ data Master side IICA0 <2> ACKD0 (ACK detection) WTIM0 <5>...
  • Page 798 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <1> to <7> in (1) Start condition ~ address ~ data in Figure 13-33 are explained below. <1> The start condition trigger is set by the master device (STT0 = 1) and a start condition (i.e. SCLA0 =1 changes SDAA0 from 1 to 0) is generated once the bus data line goes low (SDAA0).
  • Page 799 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33. Example of Slave to Master Communication (8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3) (2) Address ~ data ~ data Master side IICA0 ACKD0 (ACK detection) WTIM0 <5>...
  • Page 800 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <3> to <12> in (2) Address ~ data ~ data in Figure 13-33 are explained below. Note <3> In the slave device if the address received matches the address (SVA0 value) of a slave device , that slave device sends an ACK by hardware to the master device.
  • Page 801 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33. Example of Slave to Master Communication (8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3) (3) Data ~ data ~ stop condition Master side IICA0 ACKD0...
  • Page 802 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <8> to <19> in (3) Data ~ data ~ stop condition in Figure 13-33 are explained below. <8> The master device sets a wait status (SCLA0 = 0) at the falling edge of the 8th clock, and issues an interrupt (INTIICA0: end of transfer).

  • Page 803: Chapter 14 Multiplier And Divider/Multiply-Accumulator

    RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.1 Functions of Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator has the following functions. • 16 bits × 16 bits = 32 bits (Unsigned) • 16 bits × 16 bits = 32 bits (Signed) •...
  • Page 804 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 14-1. Block Diagram of Multiplier and Divider/Multiply-Accumulator Internal bus Multiply- Multiplication result (product) or Division accumulation multiplication result (product) while in Multiplication/division result Division result result multiply-accumulator mode control register (MDUC) (remainder) (quotient)
  • Page 805 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR (1) Multiplication/division data register A (MDAH, MDAL) The MDAH and MDAL registers set the values that are used for a multiplication or division operation and store the operation result. They set the multiplier and multiplicand data in the multiplication mode or multiply-accumulator mode, and set the dividend data in the division mode.
  • Page 806 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR (2) Multiplication/division data register B (MDBL, MDBH) The MDBH and MDBL registers set the values that are used for multiplication or division operation and store the operation result. They store the operation result (product) in the multiplication mode and multiply-accumulator mode, and set the divisor data in the division mode.
  • Page 807 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR (3) Multiplication/division data register C (MDCL, MDCH) The MDCH and MDCL registers are used to store the accumulated result while in the multiply-accumulator mode or the remainder of the operation result while in the division mode. These registers are not used while in the multiplication mode.
  • Page 808 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR The register configuration differs between when multiplication is executed and when division is executed, as follows. • Register configuration during multiplication <Multiplier A> <Multiplier B> <Product> MDAL (bits 15 to 0) × MDAH (bits 15 to 0) = [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] •...

  • Page 809: Register Controlling Multiplier And Divider/Multiply-Accumulator

    RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.3 Register Controlling Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator is controlled by using the multiplication/division control register (MDUC). (1) Multiplication/division control register (MDUC) The MDUC register is an 8-bit register that controls the operation of the multiplier and divider/multiply-accumulator.
  • Page 810 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Note The DIVST bit can only be set (1) in the division mode. In the division mode, division operation is started by setting (1) the DIVST bit. The DIVST bit is automatically cleared (0) when the operation ends. In the multiplication mode, operation is automatically started by setting the multiplier and multiplicand to multiplication/division data register A (MDAH, MDAL), respectively.

  • Page 811: Operations Of Multiplier And Divider/Multiply-Accumulator

    RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4 Operations of Multiplier and Divider/Multiply-Accumulator 14.4.1 Multiplication (unsigned) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 00H. <2> Set the multiplicand to multiplication/division data register A (L) (MDAL). <3> Set the multiplier to multiplication/division data register A (H) (MDAH).

  • Page 812: Multiplication (Signed) Operation

    RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.2 Multiplication (signed) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 08H. <2> Set the multiplicand to multiplication/division data register A (L) (MDAL). <3> Set the multiplier to multiplication/division data register A (H) (MDAH).

  • Page 813: Multiply-Accumulation (Unsigned) Operation

    RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.3 Multiply-accumulation (unsigned) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 40H. <2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (L) (MDCL). <3> Set the initial accumulated value of lower 16 bits to multiplication/division data register C (H) (MDCH).
  • Page 814 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 14-8. Timing Diagram of Multiply-Accumulation (Unsigned) Operation (2 × 3 + 3 = 9 → 32767 × 2 + 4294901762 = 0 (over flow generated)) <R> Operation clock <1> MDUC MDSM L MDCH...

  • Page 815: Multiply-Accumulation (Signed) Operation

    RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.4 Multiply-accumulation (signed) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 48H. <2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (H) (MDCH). (<3> If the accumulated value in the MDCH register is negative, the MACSF bit is set to 1.) <4>...
  • Page 816 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 14-9. Timing Diagram of Multiply-Accumulation (signed) Operation <R> (2 × 3 + (−4) = 2 → 32767 × (−1) + (−2147483647) = −2147450882 (overflow occurs.)) Operation clock <1> <3> <3> MDUC MDSM L...

  • Page 817: Division Operation

    RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.5 Division operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 80H. <2> Set the dividend (higher 16 bits) to multiplication/division data register A (H) (MDAH). <3> Set the dividend (lower 16 bits) to multiplication/division data register A (L) (MDAL).
  • Page 818 Figure 14-10. Timing Diagram of Division Operation (Example: 35 ÷ 6 = 5, Remainder 5) Operation clock MDUC <8> DIVST Counter Undefined 0000 0000 0000 0000 0000 0000 0000 0002 0008 0023 008C 0230 08C0 2300 8C00 3000 C000 0000 XXXX 0000 0023...

  • Page 819: Chapter 15 Dma Controller

    RL78/G13 CHAPTER 15 DMA CONTROLLER CHAPTER 15 DMA CONTROLLER The RL78/G13 has an internal DMA (Direct Memory Access) controller. Data can be automatically transferred between the peripheral hardware supporting DMA, SFRs, and internal RAM without via CPU. As a result, the normal internal operation of the CPU and data transfer can be executed in parallel with transfer between the SFR and internal RAM, and therefore, a large capacity of data can be processed.

  • Page 820: Configuration Of Dma Controller

    RL78/G13 CHAPTER 15 DMA CONTROLLER 15.2 Configuration of DMA Controller The DMA controller includes the following hardware. Table 15-1. Configuration of DMA Controller Item Configuration • DMA SFR address registers 0 to 3 (DSA0 to DSA3) Address registers • DMA RAM address registers 0 to 3 (DRA0 to DRA3) •...
  • Page 821 RL78/G13 CHAPTER 15 DMA CONTROLLER (2) DMA RAM address register n (DRAn) This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA channel n. Addresses of the internal RAM area other than the general-purpose registers (see table 15-2) can be set to this register.
  • Page 822 RL78/G13 CHAPTER 15 DMA CONTROLLER (3) DMA byte count register n (DBCn) This is a 10-bit register that is used to set the number of times DMA channel n executes transfer. Be sure to set the number of times of transfer to this DBCn register before executing DMA transfer (up to 1024 times).

  • Page 823: Registers Controlling Dma Controller

    RL78/G13 CHAPTER 15 DMA CONTROLLER 15.3 Registers Controlling DMA Controller DMA controller is controlled by the following registers. • DMA mode control register n (DMCn) • DMA operation control register n (DRCn) Remark n: DMA channel number (n = 0 to 3) R01UH0146EJ0100 Rev.1.00...
  • Page 824 RL78/G13 CHAPTER 15 DMA CONTROLLER (1) DMA mode control register n (DMCn) The DMCn register is a register that is used to set a transfer mode of DMA channel n. It is used to select a transfer direction, data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts DMA.
  • Page 825 RL78/G13 CHAPTER 15 DMA CONTROLLER Figure 15-4. Format of DMA Mode Control Register n (DMCn) (2/3) Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H Symbol <7> <6> <5> <4> DMCn STGn DRSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0 (When n = 0 or 1)
  • Page 826 RL78/G13 CHAPTER 15 DMA CONTROLLER Figure 15-4. Format of DMA Mode Control Register n (DMCn) (3/3) Address: F020AH (DMC2), F020BH (DMC3) After reset: 00H Symbol <7> <6> <5> <4> DMCn STGn DRSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0 (When n = 2 or 3)
  • Page 827 RL78/G13 CHAPTER 15 DMA CONTROLLER (2) DMA operation control register n (DRCn) The DRCn register is a register that is used to enable or disable transfer of DMA channel n. Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1).

  • Page 828: Operation Of Dma Controller

    RL78/G13 CHAPTER 15 DMA CONTROLLER 15.4 Operation of DMA Controller 15.4.1 Operation procedure <1> The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set the DENn bit to 1. Use 80H to write with an 8-bit manipulation instruction.

  • Page 829: Transfer Mode

    RL78/G13 CHAPTER 15 DMA CONTROLLER 15.4.2 Transfer mode The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of DMA mode control register n (DMCn). DRSn DMA Transfer Mode Transfer from SFR of 1-byte data (fixed address) to RAM (address is incremented by +1)

  • Page 830: Example Of Setting Of Dma Controller

    RL78/G13 CHAPTER 15 DMA CONTROLLER 15.5 Example of Setting of DMA Controller 15.5.1 CSI consecutive transmission A flowchart showing an example of setting for CSI consecutive transmission is shown below. • Consecutive transmission of CSI10 (256 bytes) • DMA channel 0 is used for DMA transfer.
  • Page 831 RL78/G13 CHAPTER 15 DMA CONTROLLER Figure 15-7. Example of Setting for CSI Consecutive Transmission Start DEN0 = 1 DSA0 = 44H DRA0 = FB00H DBC0 = 0100H DMC0 = 48H Setting for CSI transfer DST0 = 1 DMA is started.

  • Page 832: Consecutive Capturing Of A/D Conversion Results

    RL78/G13 CHAPTER 15 DMA CONTROLLER 15.5.2 Consecutive capturing of A/D conversion results A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below. • Consecutive capturing of A/D conversion results. • DMA channel 1 is used for DMA transfer.
  • Page 833 RL78/G13 CHAPTER 15 DMA CONTROLLER Figure 15-8. Example of Setting of Consecutively Capturing A/D Conversion Results Start DEN1 = 1 DSA1 = 1EH DRA1 = FCE0H DBC1 = 0100H DMC1 = 21H DST1 = 1 Starting A/D conversion INTAD occurs.

  • Page 834: Uart Consecutive Reception + Ack Transmission

    RL78/G13 CHAPTER 15 DMA CONTROLLER 15.5.3 UART consecutive reception + ACK transmission A flowchart illustrating an example of setting for UART consecutive reception + ACK transmission is shown below. • Consecutively receives data from UART0 and outputs ACK to P10 on completion of reception.
  • Page 835 RL78/G13 CHAPTER 15 DMA CONTROLLER Figure 15-9. Example of Setting for UART Consecutive Reception + ACK Transmission Start INTSR0 interrupt routine DEN0 = 1 DSA0 = 12H STG0 = 1 DRA0 = FE00H DBC0 = 0040H DMC0 = 00H DMA0 transfer...

  • Page 836: Holding Dma Transfer Pending By Dwaitn Bit

    RL78/G13 CHAPTER 15 DMA CONTROLLER 15.5.4 Holding DMA transfer pending by DWAITn bit When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of the CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set system, a DMA transfer can be held pending by setting the DWAITn bit to 1.

  • Page 837: Forced Termination By Software

    RL78/G13 CHAPTER 15 DMA CONTROLLER 15.5.5 Forced termination by software After the DSTn bit is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and the DSTn bit is set to 0. To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn) of DMAn, therefore, perform either of the following processes.
  • Page 838 RL78/G13 CHAPTER 15 DMA CONTROLLER Figure 15-11. Forced Termination of DMA Transfer (2/2) Example 3 • Procedure for forcibly terminating the DMA • Procedure for forcibly terminating the DMA transfer for one channel if both channels are used transfer for both channels if both channels are used...

  • Page 839: Cautions On Using Dma Controller

    RL78/G13 CHAPTER 15 DMA CONTROLLER 15.6 Cautions on Using DMA Controller (1) Priority of DMA During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending DMA transfer is started after the ongoing DMA transfer is completed. If two or more DMA requests are generated at the same time, however, their priority are DMA channel 0 >...
  • Page 840 RL78/G13 CHAPTER 15 DMA CONTROLLER (4) DMA pending instruction Even if a DMA request is generated, DMA transfer is held pending immediately after the following instructions. • CALL !addr16 • CALL $!addr20 • CALL !!addr20 • CALL • CALLT [addr5] •...

  • Page 841: Chapter 16 Interrupt Functions

    RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS CHAPTER 16 INTERRUPT FUNCTIONS The function to switch the flow of the program temporarily. The number of interrupt sources differs, depending on the product. 20-pin 24, 25- 30, 32, 40, 44- 48-pin 52-pin 64-pin 80, 100-...
  • Page 842 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (1/4) Interrupt Internal/ Vector Interrupt Source Type External Table Name Trigger Address √ √ √ √ √ √ √ √ √ √ √ √ √ √ Note 3 Maskable INTWDTI...
  • Page 843 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (2/4) Interrupt Internal/ Vector Interrupt Source Type External Table Name Trigger Address √ √ √ √ Maskable INTST1/ UART1 transmission transfer Internal 0024H INTCSI10/ end or buffer empty INTIIC10 interrupt/CSI10 transfer end or...
  • Page 844 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (3/4) Interrupt Internal/ Vector Interrupt Source Type External Table Name Trigger Address √ √ √ √ √ √ √ √ √ √ √ √ √ √ Maskable INTTM05 End of timer channel 5 count...
  • Page 845 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (4/4) Interrupt Internal/ Vector Interrupt Source Type External Table Address − − √ √ √ √ √ √ √ √ √ √ √ √ √ √ Software Execution of BRK instruction 007EH −...
  • Page 846 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus ISP1 ISP0 Vector table Interrupt Priority controller address generator request Standby release signal (B) External maskable interrupt (INTPn) Internal bus External interrupt edge...
  • Page 847 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR) Internal bus Key return mode ISP1 ISP0 register (KRM) KRMn Vector table Priority controller address generator interrupt KRn pin input detector Standby release...

  • Page 848: Registers Controlling Interrupt Functions

    RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS 16.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. • Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) • Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L) •...
  • Page 849 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2. Flags Corresponding to Interrupt Request Sources (2/4) <R> Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Source Register Register Register √ √ √ √ √ √ √ √ √ − −...
  • Page 850 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2. Flags Corresponding to Interrupt Request Sources (3/4) Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Source Register Register Register √ √ √ √ √ √ √ √ √ √ √ Note 1...
  • Page 851 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2. Flags Corresponding to Interrupt Request Sources (4/4) Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Source Register Register Register √ √ √ √ √ √ √ √ √ √ √ INTTM05...
  • Page 852 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
  • Page 853 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) (128-pin) (2/2) Address: FFFD1H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> IF2H FLIF IICAIF1 MDIF...
  • Page 854 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L)(128-pin) Address: FFFE4H After reset: FFH Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK0L PMK5 PMK4 PMK3 PMK2 PMK1...
  • Page 855 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) The priority specification flag registers are used to set the corresponding maskable interrupt priority level. A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, or 2H).
  • Page 856 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) (128-pin) (2/3) Address: FFFEBH After reset: FFH Symbol <7> <6> <5> <4> <3>...
  • Page 857 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) (128-pin) (3/3) Address: FFFDAH After reset: FFH Symbol <5> <4> <3> <2> <1>...
  • Page 858 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable registers (EGP0, EGP1), external interrupt falling edge enable registers (EGN0, EGN1) These registers specify the valid edge for INTP0 to INTP11. The EGP0, EGP1, EGN0, and EGN1 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 859 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-3. Ports Corresponding to EGPn and EGNn bits Detection Enable Bit Edge Detection Interrupt 64, 80, 52-pin 48-pin 30, 32, 24, 25- 20-pin Port Request Signal 100, 36, 40, 128-pin 44-pin √ √ √...
  • Page 860 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple interrupt servicing are mapped to the PSW.

  • Page 861: Interrupt Servicing Operations

    RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS 16.4 Interrupt Servicing Operations 16.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
  • Page 862 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-7. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending ××PR No (Low priority) (××PR ≥ (ISP1, ISP0) Interrupt request held pending Higher priority...
  • Page 863 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF 9 clocks Remark 1 clock: 1/f : CPU clock) Figure 16-9.

  • Page 864: Software Interrupt Request Acknowledgment

    RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS 16.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH, 0007FH) are loaded into the PC and branched.
  • Page 865 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request Maskable Interrupt Request Software Interrupt Priority Level 0 Priority Level 1 Priority Level 2 Priority Level 3 Request...
  • Page 866 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz...
  • Page 867 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 00) INTxx...

  • Page 868: Interrupt Request Hold

    RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS 16.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.

  • Page 869: Chapter 17 Key Interrupt Function

    RL78/G13 CHAPTER 17 KEY INTERRUPT FUNCTION CHAPTER 17 KEY INTERRUPT FUNCTION The number of key interrupt input channels differs, depending on the product. 20, 24, 25, 30, 32, 36- 40, 44-pin 48-pin 52, 64, 80, 100, 128- − Key interrupt input channels...
  • Page 870 RL78/G13 CHAPTER 17 KEY INTERRUPT FUNCTION Figure 17-1. Block Diagram of Key Interrupt INTKR KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register (KRM) Remark KR0 to KR3: 40-, 44-pin products KR0 to KR5: 48-pin products KR0 to KR7: 52-, 64-, 80-, 100-, 128-pin products R01UH0146EJ0100 Rev.1.00...

  • Page 871: Register Controlling Key Interrupt

    RL78/G13 CHAPTER 17 KEY INTERRUPT FUNCTION 17.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) KRM register controls the KR0 to KR7 signals. The KRM register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.

  • Page 872: Chapter 18 Standby Function

    RL78/G13 CHAPTER 18 STANDBY FUNCTION CHAPTER 18 STANDBY FUNCTION 18.1 Standby Function and Configuration 18.1.1 Standby function The standby function reduces the operating current of the system, and the following three modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high- speed system clock oscillator, high-speed on-chip oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues.

  • Page 873: Registers Controlling Standby Function

    RL78/G13 CHAPTER 18 STANDBY FUNCTION 18.1.2 Registers controlling standby function The standby function is controlled by the following two registers. • Oscillation stabilization time counter status register (OSTC) • Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
  • Page 874 RL78/G13 CHAPTER 18 STANDBY FUNCTION (1) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. The X1 clock oscillation stabilization time can be checked in the following case.
  • Page 875 RL78/G13 CHAPTER 18 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using the OSTS register after the STOP mode is released.

  • Page 876: Standby Function Operation

    RL78/G13 CHAPTER 18 STANDBY FUNCTION 18.2 Standby Function Operation 18.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, high-speed on-chip oscillator clock, or subsystem clock.
  • Page 877 RL78/G13 CHAPTER 18 STANDBY FUNCTION Table 18-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on...
  • Page 878 RL78/G13 CHAPTER 18 STANDBY FUNCTION Table 18-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock Item When CPU Is Operating on XT1 Clock (f When CPU Is Operating on External...
  • Page 879 RL78/G13 CHAPTER 18 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
  • Page 880 RL78/G13 CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.

  • Page 881: Stop Mode

    RL78/G13 CHAPTER 18 STANDBY FUNCTION 18.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the high-speed on-chip oscillator clock, X1 clock, or external main system clock.
  • Page 882 RL78/G13 CHAPTER 18 STANDBY FUNCTION Table 18-2. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on...
  • Page 883 RL78/G13 CHAPTER 18 STANDBY FUNCTION Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware.
  • Page 884 RL78/G13 CHAPTER 18 STANDBY FUNCTION Figure 18-5. STOP Mode Release by Interrupt Request Generation (2/2) (2) When high-speed system clock (external clock input) is used as CPU clock Interrupt request STOP instruction Standby release signal Note STOP mode release tuime...
  • Page 885 RL78/G13 CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.

  • Page 886: Snooze Mode

    RL78/G13 CHAPTER 18 STANDBY FUNCTION 18.2.3 SNOOZE mode (1) SNOOZE mode setting and operating statuses The SNOOZE mode can only be specified for CSIp, UARTq, or the A/D converter. Note that this mode can only be specified if the CPU clock is the high-speed on-chip oscillator clock.
  • Page 887 RL78/G13 CHAPTER 18 STANDBY FUNCTION Table 18-3. Operating Statuses in SNOOZE Mode STOP Mode Setting When Inputting CSIp/UARTq Data Reception Signal or A/D Converter Timer Trigger Signal While in STOP Mode Item When CPU Is Operating on High-speed on-chip oscillator clock (f...

  • Page 888: Chapter 19 Reset Function

    RL78/G13 CHAPTER 19 RESET FUNCTION CHAPTER 19 RESET FUNCTION The following seven operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-reset (POR) circuit...
  • Page 889 Figure 19-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) LVIRF TRAP WDTRF RPERF IAWRF Watchdog timer reset signal Clear Clear Clear Clear Clear Reset signal by execution of illegal instruction Reset signal by RAM parity error Reset signal by illegal-memory access RESF register read signal Reset signal to LVIM/LVIS register...
  • Page 890 RL78/G13 CHAPTER 19 RESET FUNCTION Figure 19-2. Timing of Reset by RESET Input <R> Wait for oscillation accuracy stabilization High-speed on-chip oscillator clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset period...
  • Page 891 RL78/G13 CHAPTER 19 RESET FUNCTION <R> Figure 19-4. Timing of Reset in STOP Mode by RESET Input Wait for oscillation accuracy stabilization STOP instruction execution High-speed on-chip oscillator clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected)
  • Page 892 RL78/G13 CHAPTER 19 RESET FUNCTION Table 19-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Operation stopped Operation stopped (the X1 and X2 pins are input port mode)
  • Page 893 RL78/G13 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (1/4) Hardware After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW)
  • Page 894 RL78/G13 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (2/4) Hardware Status After Reset Note 1 Acknowledgment Real-time clock Second count register (SEC) Minute count register (MIN) Hour count register (HOUR) Week count register (WEEK) Day count register (DAY)
  • Page 895 RL78/G13 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (3/4) Hardware Status After Reset Note 1 Acknowledgment Serial interface IICA IICA shift register 0, 1 (IICA0, IICA1) IICA status register 0, 1 (IICS0, IICS1) IICA flag register 0, 1 (IICF0, IICF1)
  • Page 896 RL78/G13 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (4/4) Hardware Status After Reset Note 1 Acknowledgment Note 2 Reset function Reset control flag register (RESF) Undefined Note 2 Voltage detector Voltage detection register (LVIM) Notes 2, 3...
  • Page 897 RL78/G13 CHAPTER 19 RESET FUNCTION Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. These values vary depending on the reset source.

  • Page 898: Register For Confirming Reset Source

    CHAPTER 19 RESET FUNCTION 19.1 Register for Confirming Reset Source Many internal reset generation sources exist in the RL78/G13. The reset control flag register (RESF) is used to store which source has generated the reset request. The RESF register can be read by an 8-bit memory manipulation instruction.
  • Page 899 RL78/G13 CHAPTER 19 RESET FUNCTION The status of the RESF register when a reset request is generated is shown in Table 19-3. Table 19-3. RESF Register Status When Reset Request Is Generated Reset Source RESET Input Reset by Reset by...

  • Page 900: Chapter 20 Power-On-Reset Circuit

    RL78/G13 CHAPTER 20 POWER-ON-RESET CIRCUIT CHAPTER 20 POWER-ON-RESET CIRCUIT 20.1 Functions of Power-on-reset Circuit The power-on-reset circuit (POR) has the following functions. • Generates internal reset signal at power on. ) exceeds 1.51 V ±0.03 V. The reset signal is released when the supply voltage (V •...

  • Page 901: Configuration Of Power-On-Reset Circuit

    RL78/G13 CHAPTER 20 POWER-ON-RESET CIRCUIT 20.2 Configuration of Power-on-reset Circuit The block diagram of the power-on-reset circuit is shown in Figure 20-1. Figure 20-1. Block Diagram of Power-on-reset Circuit Internal reset signal − Reference voltage source 20.3 Operation of Power-on-reset Circuit •...
  • Page 902 RL78/G13 CHAPTER 20 POWER-ON-RESET CIRCUIT Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (1/2) (1) When LVD is OFF (option byte 000C1H/010C1H: VPOC2 = 1B) <R> Supply voltage Note 1 1.6 V = 1.51 V (TYP.) = 1.50 V (TYP.)
  • Page 903 RL78/G13 CHAPTER 20 POWER-ON-RESET CIRCUIT Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (2/2) (2) When LVD is interrupt & reset mode (option byte 000C1/010C1H: LVIMDS1, LVIMDS0 = 1, 0) Supply voltage Note 4...

  • Page 904: Cautions For Power-On-Reset Circuit

    RL78/G13 CHAPTER 20 POWER-ON-RESET CIRCUIT 20.4 Cautions for Power-on-reset Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POR detection voltage ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
  • Page 905 RL78/G13 CHAPTER 20 POWER-ON-RESET CIRCUIT Figure 20-3. Example of Software Processing After Reset Release (2/2) • Checking reset source Check reset source TRAP of RESF register = 1? Reset processing by Note illegal instruction execution WDTRF of RESF register = 1?

  • Page 906: Chapter 21 Voltage Detector

    RL78/G13 CHAPTER 21 VOLTAGE DETECTOR CHAPTER 21 VOLTAGE DETECTOR 21.1 Functions of Voltage Detector The voltage detector (LVD) has the following functions. • The LVD circuit compares the supply voltage (V ) with the detection voltage (V ), and generates an...

  • Page 907: Configuration Of Voltage Detector

    RL78/G13 CHAPTER 21 VOLTAGE DETECTOR 21.2 Configuration of Voltage Detector The block diagram of the voltage detector is shown in Figure 21-1. Figure 21-1. Block Diagram of Voltage Detector N-ch Internal reset signal LVIH − LVIL INTLVI Reference Option byte (000C1H)
  • Page 908 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR (1) Voltage detection register (LVIM) This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as well as to check the LVD output mask status. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 909 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR (2) Voltage detection level register (LVIS) This register selects the voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Note1 Reset signal generation input sets this register to 00H/01H/81H Figure 21-3.
  • Page 910 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR Table 21-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H/010C1H) • When used as interrupt & reset mode Detection voltage Option byte Setting Value LVIMDS1 LVIMDS0 VPOC2 VPOC1 VPOC0 LVIS1 LVIS0...
  • Page 911 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR • When used as interrupt mode Detection voltage Option byte Setting Value LVIMDS1 LVIMDS0 VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 <R> Rising edge Falling edge 1.67 V 1.63 V 1.77 V 1.73 V 1.88 V 1.84 V 1.98 V...

  • Page 912: Operation Of Voltage Detector

    RL78/G13 CHAPTER 21 VOLTAGE DETECTOR 21.4 Operation of Voltage Detector 21.4.1 When used as reset mode • When starting operation Start in the following initial setting state. Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (V ) by using the option byte 000C1H/010C1H.
  • Page 913 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR Figure 21-4. Timing of Voltage Detector Internal Reset Signal Generation <R> (Option Byte LVIMDS1, LVIMDS0 = 1, 1) Supply voltage (V = 1.51 V (TYP.) = 1.50 V (TYP.) Time LVIMK flag Note 1 (set by software)

  • Page 914: When Used As Interrupt Mode

    RL78/G13 CHAPTER 21 VOLTAGE DETECTOR 21.4.2 When used as interrupt mode • When starting operation Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (V ) by using the option byte 000C1H/010C1H. Start in the following initial setting state.
  • Page 915 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR <R> Figure 21-5. Timing of Voltage Detector Internal Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 0, 1) Supply voltage (V = 1.51 V (TYP.) = 1.50 V (TYP.) Time LVIMK flag Note 1 (set by software)

  • Page 916: When Used As Interrupt And Reset Mode

    RL78/G13 CHAPTER 21 VOLTAGE DETECTOR 21.4.3 When used as interrupt and reset mode • When starting operation Specify the operation mode (the interrupt and reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage ) by using the option byte 000C1H/010C1H.
  • Page 917 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR Figure 21-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation <R> (Option Byte LVIMDS1, LVIMDS0 = 1, 0) Supply voltage (V LVIH LVIL = 1.51 V (TYP.) = 1.50 V (TYP.) Time LVIMK flag...
  • Page 918 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR Notes 1. The LVIMK flag is set to “1” by reset signal generation. LVIRF flag is bit 0 of the reset control flag register (RESF). The LVIRF flag may become 1 from the beginning due to the power-on waveform.

  • Page 919: Cautions For Voltage Detector

    RL78/G13 CHAPTER 21 VOLTAGE DETECTOR 21.5 Cautions for Voltage Detector (1) Checking reset source When a reset occurs, check the reset source by using the following method. Figure 21-7. Checking reset source Check reset source TRAP of RESF register = 1?
  • Page 920 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR (2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released There is some delay from the time supply voltage (V ) < LVD detection voltage (V ) until the time LVD reset has been generated.

  • Page 921: Chapter 22 Safety Functions

    This detects data errors in the flash memory by performing CRC operations. Two CRC functions are provided in the RL78/G13 that can be used according to the application or purpose of use. • High-speed CRC: The CPU can be stopped and a high-speed check executed on its entire code flash memory area during the initialization routine.

  • Page 922: Registers Used By Safety Functions

    The IEC60730 standard mandates the checking of data in the flash memory, and recommends using CRC to do it. The high-speed CRC provided in the RL78/G13 can be used to check the entire code flash memory area during the initialization routine. The high-speed CRC can be executed only when the program is allocated on the RAM and in the HALT mode of the main system clock.
  • Page 923 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS Figure 22-1. Format of Flash Memory CRC Control Register (CRC0CTL) (2/2) Address: F02F0H After reset: 00H Symbol <7> CRC0CTL CRC0EN FEA5 FEA4 FEA3 FEA2 FEA1 FEA0 FEA5 FEA4 FEA3 FEA2 FEA1 FEA0 High-speed CRC operation range...
  • Page 924 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS (2) Flash memory CRC operation result register (PGCRCL) This register is used to store the high-speed CRC operation results. The PGCRCL register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H.
  • Page 925 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS <Operation flow> Figure 22-3. Flowchart of Flash Memory CRC Operation Function (High-speed CRC) Start ; Store the expected CRC operation result ; value in the lowest 4 bytes. Set FEA5 to FEA0 bits ; CRC operation range setting ;...

  • Page 926: Crc Operation Function (General-Purpose Crc)

    CPU is operating. In the RL78/G13, a general CRC operation can be executed as a peripheral function while the CPU is operating. The general CRC can be used for checking various data in addition to the code flash memory area. The data to be checked can be specified by using software (a user-created program).
  • Page 927 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS (2) CRC data register (CRCD) This register is used to store the CRC operation result of the general-purpose CRC. The setting range is 0000H to FFFFH. After 1 clock of CPU/peripheral hardware clock (f ) has elapsed from the time CRCIN register is written, the CRC operation result is stored to the CRCD register.

  • Page 928: Ram Parity Error Detection Function

    The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit data in the RL78/G13’s RAM. By using this RAM parity error detection function, the parity bit is appended when data is written, and the parity is checked when the data is read.

  • Page 929: Ram Guard Function

    RL78/G13 CHAPTER 22 SAFETY FUNCTIONS 22.3.4 RAM guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important data stored in the RAM be protected, even if the CPU freezes. This RAM guard function is used to protect data in the specified memory space.

  • Page 930: Sfr Guard Function

    RL78/G13 CHAPTER 22 SAFETY FUNCTIONS 22.3.5 SFR guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important SFRs be protected from being overwritten, even if the CPU freezes. This SFR guard function is used to protect data in the control registers used by the port function, interrupt function, clock control function, voltage detection function, and RAM parity error detection function.

  • Page 931: Invalid Memory Access Detection Function

    RL78/G13 CHAPTER 22 SAFETY FUNCTIONS 22.3.6 Invalid memory access detection function The IEC60730 standard mandates checking that the CPU and interrupts are operating correctly. The illegal memory access detection function triggers a reset if a memory space specified as access-prohibited is accessed.
  • Page 932 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS <Control register> • Invalid memory access detection control register (IAWCTL) This register is used to control the detection of invalid memory access and RAM/SFR guard function. IAWEN bit is used in invalid memory access detection function.

  • Page 933: Frequency Detection Function

    RL78/G13 CHAPTER 22 SAFETY FUNCTIONS 22.3.7 Frequency detection function The IEC60730 standard mandates checking that the oscillation frequency is correct. The frequency detection function can detect whether the clock is operating on an abnormal frequency by comparing the internal high-speed oscillation clock or external X1 oscillation clock with the internal low-speed oscillation clock (15 kHz).
  • Page 934 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS <Control register> • Timer input select register 0 (TIS0) This register is used to select the timer input of channel 5. By selecting the internal low-speed oscillation clock for the timer input, its pulse width can be measured to determine whether the proportional relationship between the internal low-speed oscillation clock and the timer operation clock is correct.

  • Page 935: A/D Test Function

    RL78/G13 CHAPTER 22 SAFETY FUNCTIONS 22.3.8 A/D test function The IEC60730 standard mandates testing the A/D converter. The A/D test function is used to check whether the A/D converter is operating normally by executing A/D conversions of an internal voltage of 0 V, the AV voltage, and the internal reference voltage (1.45 V).
  • Page 936 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS <Control register> (1) A/D test register (ADTES) This register is used to select the A/D converter’s positive reference voltage AV the A/D converter’s negative REFP, reference voltage AV , or the analog input channel (ANIxx) as the target of A/D conversion.
  • Page 937 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS (2) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. Select ANIxx as the target of A/D conversion by ADTS register when converting the internal reference voltage (1.45 V), and specify the internal reference voltage output as the input source in the analog input channel specification register (ADS).
  • Page 938 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS Notes 1. 20-, 24-, 25-, 30-, 32-pin products: P01/ANI16 pin 20-, 24-, 25-, 30-, 32-pin products: P00/ANI17 pin Cautions 1. Be sure to clear bits 5 and 6 to 0. 2. Only rewrite the value of the ADISS bit while A/D voltage comparator operation is stopped (which is indicated by the ADCS bit of A/D converter mode register 0 (ADM0) being 0).

  • Page 939: Chapter 23 Regulator

    CHAPTER 23 REGULATOR CHAPTER 23 REGULATOR 23.1 Regulator Overview The RL78/G13 contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize the μ regulator output voltage, connect the REGC pin to V via a capacitor (0.47 to 1...

  • Page 940: Chapter 24 Option Byte

    CHAPTER 24 OPTION BYTE 24.1 Functions of Option Bytes Addresses 000C0H to 000C3H of the flash memory of the RL78/G13 form an option byte area. Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H).

  • Page 941: On-Chip Debug Option Byte (000C3H/ 010C3H)

    RL78/G13 CHAPTER 24 OPTION BYTE (3) 000C2H/010C2H Setting of flash operation mode • LV (low voltage main) mode • LS (low speed main) mode • HS (high speed main) mode Setting of the frequency of the high-speed on-chip oscillator • Select from 1 MHz, 4 MHz, 8 MHz, 12 MHz, 16 MHz, 24 MHz, and 32 MHz.

  • Page 942: Format Of User Option Byte

    RL78/G13 CHAPTER 24 OPTION BYTE 24.2 Format of User Option Byte The format of user option byte is shown below. Figure 24-1. Format of User Option Byte (000C0H/010C0H) Note 1 Address: 000C0H/010C0H WDTINIT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYON...
  • Page 943 RL78/G13 CHAPTER 24 OPTION BYTE Figure 24-2. Format of User Option Byte (000C1H/010C1H) (1/2) Note Address: 000C1H/010C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • When used as interrupt & reset mode Detection voltage Option byte Setting Value LVIMDS1 LVIMDS0...
  • Page 944 RL78/G13 CHAPTER 24 OPTION BYTE Figure 24-2. Format of User Option Byte (000C1H/010C1H) (2/2) Note Address: 000C1H/010C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • When used as interrupt mode <R> Detection voltage Option byte Setting Value LVIMDS1 LVIMDS0 VPOC2...
  • Page 945 RL78/G13 CHAPTER 24 OPTION BYTE Figure 24-3. Format of Option Byte (000C2H/010C2H) Note Address: 000C2H/010C2H CMODE1 CMODE0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 CMODE1 CMODE0 Setting of flash operation mode Operating Operating Voltage <R> Frequency Range Range LV (low voltage main) mode 1 to 4 MHz 1.6 to 5.5 V...

  • Page 946: Format Of On-Chip Debug Option Byte

    RL78/G13 CHAPTER 24 OPTION BYTE 24.3 Format of On-chip Debug Option Byte The format of on-chip debug option byte is shown below. Figure 24-4. Format of On-chip Debug Option Byte (000C3H/010C3H) Note Address: 000C3H/010C3H OCDENSET OCDERSD OCDENSET OCDERSD Control of on-chip debug operation Disables on-chip debug operation.

  • Page 947: Setting Of Option Byte

    RL78/G13 CHAPTER 24 OPTION BYTE 24.4 Setting of Option Byte The user option byte and on-chip debug option byte can be set using the assembler linker option, in addition to describing to the source. When doing so, the contents set by using the linker option take precedence, even if descriptions exist in the source, as mentioned below.

  • Page 948: Chapter 25 Flash Memory

    CHAPTER 25 FLASH MEMORY The RL78/G13 incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory includes the “code flash memory”, in which programs can be executed, and the “data flash memory”, an area for storing data.

  • Page 949: Writing To Flash Memory By Using Flash Memory Programmer

    Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming The contents of the flash memory can be rewritten after the RL78/G13 has been mounted on the target system. The connectors that connect the dedicated flash memory programmer must be mounted on the target system.
  • Page 950 RL78/G13 CHAPTER 25 FLASH MEMORY <R> Table 25-1. Wiring Between RL78/G13 and Dedicated Flash Memory Programmer Pin Configuration of Dedicated Flash Memory Pin Name Pin No. Programmer 20-pin 24-pin 25-pin 30-pin 32-pin 36-pin 40-pin 44-pin Signal Name Pin Function SSOP...

  • Page 951: Programming Environment

    RL78/G13 CHAPTER 25 FLASH MEMORY 25.1.1 Programming Environment The environment required for writing a program to the flash memory of the RL78/G13 is illustrated below. Figure 25-1. Environment for Writing Program to Flash Memory PG-FP5, FL-PR5 Note RS-232C , EV...

  • Page 952: Writing To Flash Memory By Using External Device (That Incorporates Uart)

    RL78/G13 UART (TOOLTxD, TOOLRxD) (such as microcontroller TOOL0 and ASIC) Processing to write data to or delete data from the RL78/G13 by using an external device is performed on-board. Off- board writing is not possible. R01UH0146EJ0100 Rev.1.00 Sep 22, 2011...

  • Page 953: Communication Mode

    RL78/G13 CHAPTER 25 FLASH MEMORY 25.2.2 Communication Mode Communication between the external device and the RL78/G13 is established by serial communication using the <R> TOOLTxD and TOOLRxD pins via the dedicated UART of the RL78/G13. <R> Transfer rate: 1 M, 500 k, 250 k, 115.2kbps Figure 25-4.

  • Page 954: Connection Of Pins On Board

    When used as an output pin: When this pin is used via pull-down resistors, use the 500 kΩ or more resistors. Remark The SAU and IICA pins are not used for communication between the RL78/G13 and dedicated flash memory programmer, because single-line UART (TOOL0 pin) is used.

  • Page 955: Port Pins

    RL78/G13 CHAPTER 25 FLASH MEMORY 25.3.3 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status...

  • Page 956: Data Flash

    25.4 Data Flash 25.4.1 Data flash overview <R> In addition to 16 to 512 KB of code flash memory, the RL78/G13 with data flash includes 4/8 KB of data flash memory for storing data. F F F F F H...

  • Page 957: Register Controlling Data Flash Memory

    RL78/G13 CHAPTER 25 FLASH MEMORY An overview of the data flash memory is provided below. • The data flash memory can be written to by using the flash memory programmer or an external device • Programming is performed in 8-bit units <R>...

  • Page 958: Procedure For Accessing Data Flash Memory

    RL78/G13 CHAPTER 25 FLASH MEMORY 25.4.3 Procedure for accessing data flash memory The data flash memory is initially stopped after a reset ends and cannot be accessed (read or programmed). To access the memory, perform the following procedure: <1> Write 1 to bit 0 (DFLEN) of the data flash control register (DFLCTL).

  • Page 959: Programming Method

    RL78/G13 CHAPTER 25 FLASH MEMORY 25.5 Programming Method 25.5.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 25-7. Flash Memory Manipulation Procedure Start Flash memory programming Controlling TOOL0 pin and RESET pin mode is set...

  • Page 960: Flash Memory Programming Mode

    CHAPTER 25 FLASH MEMORY 25.5.2 Flash memory programming mode To rewrite the contents of the flash memory, set the RL78/G13 in the flash memory programming mode. To enter the mode, set as follows. <When programming by using the dedicated flash memory programmer>...

  • Page 961: Selecting Communication Mode

    Remarks 1. Using both the wide voltage mode and full speed mode imposes no restrictions on writing, deletion, or verification. 2. For details about communication commands, see 25.5.4 Communication commands. 25.5.3 Selecting communication mode Communication mode of the RL78/G13 as follows. Table 25-6. Communication Modes Note 1 Communication...

  • Page 962: Communication Commands

    The RL78/G13 communicates with the dedicated flash memory programmer or external device by using commands. The signals sent from the flash memory programmer or external device to the RL78/G13 are called commands, and the signals sent from the RL78/G13 to the dedicated flash memory programmer or external device are called response.

  • Page 963: Description Of Signature Data

    25.5.5 Description of signature data <R> When the “silicon signature” command is performed, the RL78/G13 information (such as the part number, flash memory configuration, and programming firmware version) can be obtained. Table 25-9 and 25-10 show signature data list and example of signature data list.

  • Page 964: Security Settings

    CHAPTER 25 FLASH MEMORY 25.6 Security Settings The RL78/G13 supports a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command. The security setting is valid when the programming mode is set next.
  • Page 965 RL78/G13 CHAPTER 25 FLASH MEMORY Table 25-11. Relationship Between Enabling Security Function and Command (1) During on-board/off-board programming Valid Security Executed Command Block Erase Write Note Can be performed. Prohibition of block erase Blocks cannot be erased. Prohibition of writing Blocks can be erased.

  • Page 966: Flash Memory Programming By Self-Programming

    25.7 Flash Memory Programming by Self-Programming The RL78/G13 supports a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the RL78/G13 self-programming library, it can be used to upgrade the program in the field.
  • Page 967 RL78/G13 CHAPTER 25 FLASH MEMORY The following figure illustrates a flow of rewriting the flash memory by using a self programming library. Figure 25-10. Flow of Self Programming (Rewriting Flash Memory) Flash memory control start Initialize flash environment Flash shield window setting...

  • Page 968: Boot Swap Function

    1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmware of the RL78/G13, so that boot cluster 1 is used as a boot area.
  • Page 969 RL78/G13 CHAPTER 25 FLASH MEMORY Figure 25-12. Example of Executing Boot Swapping Block number Erasing block 4 Erasing block 5 Erasing block 6 Erasing block 7 Program Program Program Program Program Program Program Boot Program Program cluster 1 Program 0 1 0 0 0 H...

  • Page 970: Flash Shield Window Function

    RL78/G13 CHAPTER 25 FLASH MEMORY 25.7.2 Flash shield window function The flash shield window function is provided as one of the security functions for self programming. It disables writing to and erasing areas outside the range specified as a window only during self programming.

  • Page 971: Chapter 26 On-Chip Debug Function

    Serial communication is performed by using a single-line UART that uses the TOOL0 pin. Caution The RL78/G13 has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed.

  • Page 972: On-Chip Debug Security Id

    26.2 On-Chip Debug Security ID The RL78/G13 has an on-chip debug operation control bit in the flash memory at 000C3H (see CHAPTER 24 OPTION BYTE) and an on-chip debug security ID setting area at 000C4H to 000CDH, to prevent third parties from reading memory content.
  • Page 973 RL78/G13 CHAPTER 26 ON-CHIP DEBUG FUNCTION <R> Figure 26-2. Memory Spaces Where Debug Monitor Programs Are Allocated Code flash memory Internal RAM Use prohibited SFR area Note 1 (512 bytes or Note 2 256 bytes Stack area for debugging Internal RAM...

  • Page 974: Chapter 27 Bcd Correction Circuit

    RL78/G13 CHAPTER 27 BCD CORRECTION CIRCUIT CHAPTER 27 BCD CORRECTION CIRCUIT 27.1 BCD Correction Circuit Function The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code with this circuit. The decimal correction operation result is obtained by performing addition/subtraction having the A register as the operand and then adding/ subtracting the BCD correction result register (BCDADJ).

  • Page 975: Bcd Correction Circuit Operation

    RL78/G13 CHAPTER 27 BCD CORRECTION CIRCUIT 27.3 BCD Correction Circuit Operation The basic operation of the BCD correction circuit is as follows. (1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a BCD code value <1>...
  • Page 976 RL78/G13 CHAPTER 27 BCD CORRECTION CIRCUIT (2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using a BCD code value <1> The BCD code value from which subtraction is performed is stored in the A register.

  • Page 977: Chapter 28 Instruction Set

    RL78/G13 CHAPTER 28 INSTRUCTION SET CHAPTER 28 INSTRUCTION SET This chapter lists the instructions in the RL78 microcontroller instruction set. For details of each operation and <R> operation code, refer to the separate document RL78 Microcontrollers User’s Manual: software. R01UH0146EJ0100 Rev.1.00...

  • Page 978: Conventions Used In Operation List

    RL78/G13 CHAPTER 28 INSTRUCTION SET 28.1 Conventions Used in Operation List 28.1.1 Operand identifiers and specification methods Operands are described in the “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them.

  • Page 979: Description Of Operation Column

    RL78/G13 CHAPTER 28 INSTRUCTION SET 28.1.2 Description of operation column The operation when the instruction is executed is shown in the “Operation” column using the following symbols. Table 28-2. Symbols in “Operation” Column Symbol Function A register; 8-bit accumulator X register...

  • Page 980: Description Of Flag Operation Column

    RL78/G13 CHAPTER 28 INSTRUCTION SET 28.1.3 Description of flag operation column The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols. Table 28-3. Symbols in “Flag” Column Symbol Change of Flag Value...

  • Page 981: Operation List

    RL78/G13 CHAPTER 28 INSTRUCTION SET <R> 28.2 Operation List Table 28-5. Operation List (1/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − r ← byte 8-bit data r, #byte transfer PSW ← byte ×...
  • Page 982 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (2/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − A ← sfr 8-bit data A, sfr transfer − sfr ← A sfr, A A ← (DE) A, [DE] (DE) ←...
  • Page 983 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (3/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY A ← (HL + B) 8-bit data A, [HL+B] transfer − (HL + B) ← A [HL+B], A A ←...
  • Page 984 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (4/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − A ←→ (HL+B) 8-bit data A, [HL+B] transfer − A ←→ ((ES, HL)+B) A, ES:[HL+B] −...
  • Page 985 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (5/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY AX ← (DE) 16-bit MOVW AX, [DE] data − (DE) ← AX [DE], AX transfer AX ← (ES, DE) AX, ES:[DE] (ES, DE) ←...
  • Page 986 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (6/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY BC ← (addr16) 16-bit MOVW BC, !addr16 data BC ← (ES, addr16) BC, ES:!addr16 transfer DE ← (addr16) DE, !addr16 DE ←...
  • Page 987 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (7/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − A, CY ← A+byte+CY 8-bit ADDC A, #byte × × × operation − (saddr), CY ← (saddr) +byte+CY saddr, #byte ×...
  • Page 988 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (8/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − A, CY ← A – byte – CY 8-bit SUBC A, #byte × × ×...
  • Page 989 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (9/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − A ← A∨byte 8-bit A, #byte × operation − (saddr) ← (saddr)∨byte saddr, #byte ×...
  • Page 990 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (10/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − 8-bit A, #byte A – byte × × × operation !addr16, #byte (addr16) – byte ×...
  • Page 991 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (11/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − AX, CY ← AX+word 16-bit ADDW AX, #word × × × operation − AX, CY ← AX+AX AX, AX ×...
  • Page 992 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (12/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − r ← r+1 Increment/ × × decrement − (addr16) ← (addr16)+1 !addr16 × × −...
  • Page 993 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (13/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − ← A ← A Rotate A, 1 (CY, A )×1 × − ← A ← A...
  • Page 994 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (14/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − CY ← CY ∨ A.bit XOR1 CY, A.bit × manipulate − CY ← CY ∨ PSW.bit CY, PSW.bit...
  • Page 995 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (15/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − (SP – 2) ← (PC+2) , (SP – 3) ← (PC+2) CALL Call/ (SP – 4) ← (PC+2) , PC ←...
  • Page 996 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (16/17) Instruction Mnemon Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − (SP − 1) ← PSW, (SP − 2) ← 00H, Stack PUSH manipulate SP ← SP−2 −...
  • Page 997 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (17/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY − PC ← PC + 4 + jdisp8 if (saddr).bit = 0 Note3 Condition saddr.bit, $addr20 al branch −...

  • Page 998: Chapter 29 Electrical Specifications

    <R> CHAPTER 29 ELECTRICAL SPECIFICATIONS Cautions 1. The RL78/G13 have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed.

  • Page 999: Absolute Maximum Ratings

    RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 2.1.1 20-pin products to 2.1.14 128-pin products, and 2.1.15 Pins for each product (pins other than port pins). <R> 29.2 Absolute Maximum Ratings Absolute Maximum Ratings (T = 25°C) (1/2)
  • Page 1000 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 2.1.1 20-pin products to 2.1.14 128-pin products, and 2.1.15 Pins for each product (pins other than port pins). Absolute Maximum Ratings (T = 25°C) (2/2)

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