Renesas RL78 Series User Manual page 902

RL78/G1D
Edition
Rev.1.10
Deletion of remark 2 in (7) Delay counter
Deletion of remark 2 in Table 7-2. Timer I/O Pins provided in Each Product
Change of notes of Figure 7-2. Internal Block Diagram of Channels 0, 2, 4, 6 of Timer
Array Unit 0
Addition of remark to Figure 7-3. Internal Block Diagram of Channel 1 and 3 of Timer
Array Unit 0
Change of Figure 7-4. Internal Block Diagram of Channel 5 of Timer Array Unit 0, and
Figure 7-5. Internal Block Diagram of Channel 7 of Timer Array Unit 0
Change of remark 2 of Figure 7-10. Format of Timer Clock Select register m (TPSm)
(1/2)
Change of Figure 7-11. Format of Timer Mode Register mn (TMRmn)
Change of caution of Figure 7-16. Format of Timer Input Select register 0 (TIS0)
Change of description in 7.3.10 Timer output register 0 (TO0)
Change of Figure 7-19. Format of Timer Output Level register 0 (TOL0)
Change of Figure 7-20. Format of Timer Output Mode register 0 (TOM0)
Change of Figure 7-21. Format of Noise Filter Enable Register 1 (NFEN1)
Change of description in 7.3.14 Registers controlling port functions of pins to be used
for timer I/O
Change of description in 7.5.1 Count clock (f
Change of remark 2 of Figure 7-31. TO0n Pin Output Status at Toggle Output (TOM0n
= 0)
Change of remark 2 of Figure 7-32. TO0n Pin Output Status at Toggle Output (TOM0n
= 1)
Deletion of caution in Figure 7-36. TO0n Pin Statuses by Collective Manipulation of
TO0n Bit
Change of Figure 7-56. Block Diagram of Operation as Input Signal High-/Low-Level
Width Measurement
Change of Figure 7-60. Block Diagram of Operation as Delay Counter
Addition of note 1 and 2 to Figure 8-5. Format of Real-time Clock Control Register 1
(RTCC1) (2/2)
Change of description in 10.5 Cautions of Clock Output/Buzzer Output Controller
Addition and change of description in 12.1 Function of A/D Converter
Change of Figure 12-3. Format of A/D Converter Mode Register 0 (ADM0)
Change of Table 12-2. Setting and Clearing Conditions for ADCS Bit
Change of Figure 12-4. Timing Chart When A/D Voltage Comparator Is Used
Change of note 1 of Table 12-3. A/D Conversion Time Selection
Change of Figure 12-11. Format of Analog Input Channel Specification Register (ADS)
Change of description in 12.6.1 Software trigger mode (sequential conversion mode)
Change of Figure 12-17. Example of Software Trigger Mode (Sequential Conversion
Mode) Operation Timing
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Description
)
TCLK
APPENDIX A REVISION HISTORY
Chapter
CHAPTER 7 TIMER
ARRAY UNIT
CHAPTER 8 REAL-TIME
CLOCK
CHAPTER 10 CLOCK
OUTPUT/BUZZER
OUTPUT CONTROLLER
CHAPTER 12 A/D
CONVERTER
(2/7)
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