Renesas RL78 Series User Manual page 276

RL78/G1D
Figure 7-74. Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs)
Master channel
(interval timer mode)
CKm1
Operation clock
CKm0
TSmn
Slave channel 1
(one-count mode)
CKm1
Operation clock
CKm0
Slave channel 2
(one-count mode)
CKm1
Operation clock
CKm0
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4)
p: Slave channel number 1, q: Slave channel number 2
n < p < q 7 (Where p and q are integers greater than n)
≤
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CHAPTER 7 TIMER ARRAY UNIT
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Timer counter
register mp (TCRmp)
Timer data
register mp (TDRmp)
Timer counter
register mq (TCRmq)
Timer data
register mq (TDRmq)
Interrupt
Interrupt signal
controller
(INTTMmn)
Output
TO0p pin
controller
Interrupt
Interrupt signal
controller
(INTTMmp)
Output
TO0q pin
controller
Interrupt
Interrupt signal
controller
(INTTMmq)
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