Renesas RL78 Series User Manual page 871

RL78/G1D
CSI mode serial transfer timing (master mode) (during communication at different potential)
SCKp
SIp
SOp
CSI mode serial transfer timing (master mode) (during communication at different potential)
SCKp
SIp
SOp
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V
mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port
output mode register g (POMg).
Remark p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM
number (g = 1)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t
KL1
t
KSO1
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t
t
KSO1
CHAPTER 30 ELECTRICAL SPECIFICATIONS
t
KCY1
t
t
SIK1
KSI1
Input data
t
KCY1
t
KL1
KH1
t
t
SIK1
KSI1
Input data
Output data
t
KH1
Output data
tolerance)
DD
850