Renesas RL78 Series User Manual page 267

RL78/G1D
Figure 7-68. Operation Procedure of One-Shot Pulse Output Function (2/2)
Operation Sets the TOE0p bit (slave) to 1 (only when operation is
start resumed).
The TSmn (master) and TSmp (slave) bits of timer
channel start register m (TSm) are set to 1 at the same
time.
The TSmn and TSmp bits automatically return to 0
because they are trigger bits.
Count operation of the master channel is started by start
trigger detection of the master channel.
● Detects the TImn pin input valid edge.
● Sets the TSmn bit of the master channel to 1 by
Note
software .
Note Do not set the TSmn bit of the slave channel to 1.
During Set values of only the CISmn1 and CISmn0 bits of the
operation TMRmn register can be changed.
Set values of the TMRmp, TDRmn, TDRmp registers,
TOM0n, TOM0p, TOL0n, and TOL0p bits cannot be
changed.
The TCRmn and TCRmp registers can always be read.
The TSRmn and TSRmp registers are not used.
Set values of the TO0 and TOE0 registers by slave
channel can be changed.
Operation The TTmn (master) and TTmp (slave) bits are set to 1 at
stop the same time.
The TTmn and TTmp bits automatically return to 0
because they are trigger bits.
The TOE0p bit of slave channel is cleared to 0 and value
is set to the TO0p bit.
TAU To hold the TO0p pin output level
stop Clears the TO0p bit to 0 after the value to
be held is set to the port register.
When holding the TO0p pin output level is not
necessary
Setting not required.
The TAUmEN bit of the PER0 register is cleared to 0.
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Software Operation
7)
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CHAPTER 7 TIMER ARRAY UNIT
Hardware Status
The TEmn and TEmp bits are set to 1 and the master
channel enters the start trigger detection (the valid edge of
the TImn pin input is detected or the TSmn bit of the
master channel is set to 1) wait status.
Counter stops operating.
Master channel starts counting.
Master channel loads the value of the TDRmn register to
timer count register mn (TCRmn) by the start trigger
detection (the valid edge of the TImn pin input is detected
or the TSmn bit of the master channel is set to 1), and the
counter starts counting down. When the count value
reaches TCRmn = 0000H, the INTTMmn output is
generated, and the counter stops until the next start trigger
detection.
The slave channel, triggered by INTTMmn of the master
channel, loads the value of the TDRmp register to the
TCRmp register, and the counter starts counting down.
The output level of TO0p becomes active one count clock
after generation of INTTMmn from the master channel. It
becomes inactive when TCRmp = 0000H, and the
counting operation is stopped.
After that, the above operation is repeated.
TEmn, TEmp = 0, and count operation stops.
The TCRmn and TCRmp registers hold count value and
stop.
The TO0p output is not initialized but holds current
status.
The TO0p pin outputs the TO0p set level.
The TO0p pin output level is held by port function.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TO0p bit is cleared to 0 and the TO0p pin is set to
port mode.)
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