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Section 2 CPU
16 ÷ 8-bit register-register divide: 12 states
16 × 16-bit register-register multiply: 3 states
32 ÷ 16-bit register-register divide: 20 states
• Two CPU operating modes
Normal mode*
Advanced mode
• Power-down state
Transition to power-down state by the SLEEP instruction
CPU clock speed selection
Note: * Normal mode is not available in this LSI.
2.1.1
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register is supported by the H8S/2600 CPU only.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600
CPU only.
• The number of execution states of the MULXU and MULXS instructions;
Instruction
MULXU
MULXS
CLRMAC
LDMAC
STMAC
Note:
This becomes one state greater immediately after a MAC instruction.
*
In addition, there are differences in address space, CCR and EXR register functions,
and power-down modes, etc., depending on the model.
Rev. 1.00 Apr. 28, 2008 Page 30 of 994
REJ09B0452-0100
Mnemonic
MULXU.B Rs, Rd
MULXU.W Rs, ERd
MULXS.B Rs, Rd
MULXS.W Rs, ERd
CLRMAC
LDMAC ERs,MACH
LDMAC ERs,MACL
STMAC MACH,ERd
STMAC MACl,ERd
Execution States
H8S/2600
2*
2*
3*
3*
1*
1*
1*
1*
1*
H8S/2000
12
20
13
21
Not supported
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