D.2 Pin States At Reset - Renesas F-ZTAT H8 Series Hardware Manual

Appendix D Pin States
D.2 Pin States at Reset
Reset in T1 State: Figure D.1 is a timing diagram for the case in which RES goes low during the
T1 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance
state. The address bus is initialized to the low output level 0.5 state after the low level of RES is
sampled. Sampling of RES takes place at the fall of the system clock (φ).
φ
RES
Internal
reset signal
Address bus
CS
0
CS to CS
7 1
AS
RD (read access)
HWR, LWR
(write access)
Data bus
(write access)
I/O port
Figure D.1 Reset during Memory Access (Reset during T1 State)
Rev. 7.00 Sep 21, 2005 page 872 of 878
REJ09B0259-0700
Access to external address
T1
High
High
High
T2 T3
H'000000
High impedance
High impedance
High impedance