Slave Receive Operation; Figure 17.9 Master Receive Mode Operation Timing Example (2) (Mls = Ackb = 0, Wait = 1) - Renesas H8S/2158 User Manual

2
Section 17 I C Bus Interface (IIC)
SCL
(master output) 8
SDA
Bit 0
(slave output)
Data 2
[8]
SDA
(master output)
IRIC
IRTR
ICDR
Data 1
User processing
[9] IRIC clear
Figure 17.9 Master Receive Mode Operation Timing Example (2)
17.5.4

Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The reception procedure and operations in slave
receive mode are described below.
1. Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR
according to the operating mode.
2. When the start condition output by the master device is detected, the BBSY flag in ICCR is set
to 1.
3. When the slave address matches in the first frame following the start condition, the device
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit in ICCR remains cleared to 0, and slave receive operation is performed.
4. At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an
acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in
ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has
been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag
has been set to 1, the slave device drives SCL low from the fall of the receive clock until data
is read into ICDR.
5. Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0.
Rev. 3.00 Jan 25, 2006 page 522 of 872
REJ09B0286-0300
9 1 2 3
Bit 7 Bit 6 Bit 5
[5]
A
[7] IRIC clear
[6] ICDR read
(Data 2)
(MLS = ACKB = 0, WAIT = 1)
4 5 6 7
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 3
Data 2
8 9 1
Bit 7
[8] [5]
A
Data 3
[6] ICDR read
(Data 3)
[9] IRIC clear
[7] IRIC clear
2
Bit 6
Data 4