Slave Receive Operation; Figure 15.10 Slave Transmit Mode Operation Timing (2) - Renesas H8 Series Hardware Manual

SCL
9
(Master output)
SDA
A
(Master output)
SCL
(Slave output)
SDA
(Slave output)
TDRE
TEND
TRS
ICDRT
ICDRS
ICDRR
User
processing

Figure 15.10 Slave Transmit Mode Operation Timing (2)

15.4.5

Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 15.11 and 15.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address and R/W, it is not used.)
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
1 2 3 4
Bit 7 Bit 6 Bit 5 Bit 4
Data n
[3] Clear TEND
Section 15 I
Slave transmit mode
5 6 7 8
Bit 3 Bit 2 Bit 1 Bit 0
[4] Read ICDRR (dummy read)
after clearing TRS
Rev. 3.00 Sep. 14, 2006 Page 261 of 408
2
C Bus Interface 2 (IIC2)
Slave receive
mode
9
A
[5] Clear TDRE
REJ09B0105-0300