Slave Receive Operation; Figure 17.10 Operation Timing In Slave Transmit Mode (2) - Renesas H8S/2437 Hardware Manual

SCL
9
(master output)
SDA
A
(master output)
SCL
(slave output)
SDA
(slave output)
TDRE
TEND
TRS
ICDRT
ICDRS
ICDRR
User
processing

Figure 17.10 Operation Timing in Slave Transmit Mode (2)

17.4.5

Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The operation timings in slave receive mode are
shown in figures 17.11 and 17.12. The reception procedure and operations in slave receive mode
are described below.
1. Set the ICE bit in ICCRA to 1. Set the WAIT bit in ICMR and the CKS3 to CKS0 bits in
ICCRA to 1 (initial setting). Set the MST and TRS bits in ICCRA to select slave receive mode,
and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address and R/W, it is not used.)
3. Read ICDRR every time RDRF is set. If the 8th receive clock pulse falls while RDRF is 1,
SCL is fixed low until RDRF is cleared. The change of the acknowledge before clearing
RDRF, to be returned to the master device, is reflected to the next transfer frame.
Rev. 1.00, 09/03, page 498 of 704
1 2 3 4
Bit 7 Bit 6 Bit 5 Bit 4
Data n
[3] Clear TEND
Slave transmit mode
5 6 7 8
Bit 3 Bit 2 Bit 1 Bit 0
[4] Read ICDRR (dummy read)
after clearing TRS
Slave receive
mode
9
A/
[5] Clear TDRE