Renesas H8S Series Hardware Manual page 994

TSR2—Timer Status Register 2
Bit :
Initial value :
Read/Write :
Note: Can only be written with 0 for flag clearing.
*
Rev.6.00 Oct.28.2004 page 966 of 1016
REJ09B0138-0600H
7
6 5 4
TCFD — TCFU TCFV
1 1 0 0
R — R/(W)* R/(W)*
Overflow Flag
0
1
Underflow Flag
0
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
1 [Setting condition]
When the TCNT value underflows (changes from H'0000 to H'FFFF)
Count Direction Flag
0 TCNT counts down
1 TCNT counts up
H'FFF5
3 2 1
— — TGFB TGFA
0 0 0
— — R/(W)* R/(W)*
Input Capture/Output Compare Flag A
0
1
Input Capture/Output Compare Flag B
0
[Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL
bit of MRB in DTC is 0
• When 0 is written to TGFB after reading
TGFB = 1
1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
output compare register
• When TCNT value is transferred to TGRB by input
capture signal while TGRB is functioning as input
capture register
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
TPU2
0
0
[Clearing conditions]
• When DTC is activated by TGIA interrupt
while DISEL bit of MRB in DTC is 0
• When DMAC is activated by TGIA interrupt
while DTA bit of DMABCR in DMAC is 1
• When 0 is written to TGFA after reading
TGFA = 1
[Setting conditions]
• When TCNT = TGRA while TGRA is
functioning as output compare register
• When TCNT value is transferred to TGRA by
input capture signal while TGRA is functioning
as input capture register