Renesas H8S Series Hardware Manual page 993

TIER2—Timer Interrupt Enable Register 2
Bit
Initial value
Read/Write
:
7 6 5
TTGE — TCIEU
:
0 1 0
:
R/W — R/W
Underflow Interrupt Enable
0
1
A/D Conversion Start Request Enable
0 A/D conversion start request generation disabled
1 A/D conversion start request generation enabled
H'FFF4
4 3 2
TCIEV — —
0 0 0
R/W — —
Overflow Interrupt Enable
0 Interrupt requests (TCIV) by TCFV disabled
1 Interrupt requests (TCIV) by TCFV enabled
Interrupt requests (TCIU) by TCFU disabled
Interrupt requests (TCIU) by TCFU enabled
TPU2
1 0
TGIEB TGIEA
0 0
R/W R/W
TGR Interrupt Enable A
0 Interrupt requests (TGIA)
by TGFA bit disabled
1 Interrupt requests (TGIA)
by TGFA bit enabled
TGR Interrupt Enable B
0 Interrupt requests (TGIB)
by TGFB bit disabled
1 Interrupt requests (TGIB)
by TGFB bit enabled
Rev.6.00 Oct.28.2004 page 965 of 1016
REJ09B0138-0600H