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M16C/6N5 Group
Programmable I/O Ports
The programmable input/output ports (hereafter referred to simply as "I/O ports") consist of 87 lines P0 to
P10 (except P8
). Each port can be set for input or output every line by using a direction register, and can
5
also be chosen to be or not be pulled high every 4 lines. P8
up resistor. Port P8
5
P8_5 bit.
Figures 1.20.1 to 1.20.5 show the I/O ports. Figure 1.20.6 shows the I/O pins.
Each pin functions as an I/O port, a peripheral function input/output, or a bus control pin.
For details on how to set peripheral functions, refer to each functional description in this manual. If any pin
is used as a peripheral function input or D-A converter output pin, set the direction bit for that pin to "0" (input
mode). Any pin used as an output pin for peripheral functions other than the D-A converter is directed for
output no matter how the corresponding direction bit is set.
When using any pin as a bus control pin, refer to "Bus Control."
(1) Port Pi Direction Register (PDi Register, i = 0 to 10)
Figure 1.20.7 shows the PDi register.
This register selects whether the I/O port is to be used for input or output. The bits in this register correspond
one for one to each port.
During memory expansion and microprocessor modes, the PDi registers for the pins functioning as bus
control pins (A
to A
0
BCLK) cannot be modified.
No direction register bit for P8
(2) Port Pi Register (Pi Register, i = 0 to 10)
Figure 1.20.8 shows the Pi register.
Data input/output to and from external devices are accomplished by reading and writing to the Pi register.
The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For
ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register,
and data can be written to the port latch by writing to the Pi register.
For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and
data can be written to the port latch by writing to the Pi register. The data written to the port latch is output
from the pin. The bits in the Pi register correspond one for one to each port.
During memory expansion and microprocessor modes, the PDi registers for the pins functioning as bus
control pins (A
to A
0
BCLK) cannot be modified.
(3) Pull-up Control Register j (PURj Register, j = 0 to 2)
Figure 1.20.9 shows the PURj register.
The PURj register bits can be used to select whether or not to pull the corresponding port high in 4 bit
units. The port selected to be pulled high has a pull-up resistor connected to it when the direction bit is set
for input mode.
However, the pull-up control register has no effect on P0 to P3, P4
expansion and microprocessor modes. Although the register contents can be modified, no pull-up resistors
are connected.
(4) Port Control Register (PCR Register)
Figure 1.20.10 shows the PCR register.
When the P1 register is read after setting the PCR register's PCR0 bit to "1", the corresponding port latch
can be read no matter how the PD1 register is set.
Tables 1.20.1 and 1.20.2 list an example connection of unused pins. Figure 1.20.11 shows an example
connection of unused pins.
Rev.1.00
2003.05.30
page 228
_______
shares the pin with NMI, so that the NMI input level can be read from the P8 register
, D
to D
, CS
to CS
19
0
15
0
3
is available.
5
, D
to D
, CS
to CS
19
0
15
0
3
is an input-only port and does not have a pull-
5
______
_______ _________ ______
__________________
, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
_______ _________ ______
__________________
, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
Programmable I/O Ports
_________ _________
_________
_________ _________
_________
to P4
, and P5 during memory
0
3
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