VeEX MPA User Manual page 762

MPA_e_manual_D07-00-129P_RevA00
c. An error will appear stating "Connected to MCH without BITS/SETS
hardware" will appear if you enter the IP Address of an older MCH card
that does not support the External Clock.
5. Select Chassis Clock. The Chassis Clock dialog box appears.
6. Select one of the following External or Internal clock reference options.
a. The External Clock In Status will show Locked as the synchronized to
the Clock In.
Chassis Clock
Options
External (BITS
1.544 Mbps
In/Out)
External (SETS
2.048 Mbps
In/Out)
External (2.048
MHz Clock In/Out)
Internal (No
Output)
Internal (BITS
1.544 Mbps
In/Out)
Description
Synchronizes the transmitted signals to the BITS (Building
Integrated Timing Supply) clock input, which is 1.544 Mbps.
Chassis (BITS) option appears in the Clock Reference menu,
and CLK:BITS displays in the Quick LED Status area when
selected.
Synchronizes the transmitted signals to the SETS
(Synchronous Equipment Timing Source) clock input, which is
2.048 Mbps.
Chassis (SETS) option appears in the Clock Reference menu,
and CLK:SETS displays in the Quick LED Status area when
selected.
This synchronizes the transmitted signals to a 2.048 MHz sine-
wave clock input.
Chassis (2.048 MHz) option appears in the Clock Reference
menu, and CLK:2.048 MHz displays in the Quick LED Status
area when selected.
The transmit signals derive their data's timing source from the
system's Internal Stratum 3 clock source.
Chassis (Internal) option appears in the Clock Reference
menu, and CLK:INT displays in the Quick LED Status area
when selected.
There is no timing signal on the Clock output.
The transmit signals derive their data's timing source from the
system's Internal Stratum 3 clock source.
Chassis (Internal) option appears in the Clock Reference
menu, and CLK:INT displays in the Quick LED Status area
when selected.
The Clock output is a 1.544 Mbps BITS clock.
Misc Screen
762