VeEX MPA User Manual page 173

MPA_e_manual_D07-00-129P_RevA00
Protocol Tabs
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MLD Miscellaneous Information
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Saving and Printing Statistics and Settings Reports
MLD Miscellaneous Information
Block Lock
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Each block lock process looks for 64 valid sync headers in a row to declare lock.
A valid sync header is either a 01 or a 10.
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Once in lock, the lock process looks for 65 invalid sync headers within a 1024
sync window to declare out of lock. An invalid sync header is either a 11 or a 00.
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Once block lock is achieved on a lane, then the alignment marker process starts.
Sync Header
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Blocks consist of 66 bits. The first two bits of a block are the synchronization
header (sync header)
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Blocks are either data blocks or control blocks. The sync header is 01 for data
blocks and 10 for control blocks. Thus, there is always a transition between the
first two bits of a block
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The remainder of the block contains the payload. The payload is scrambled and
the sync header bypasses the scrambler. Therefore, the sync header is the only
position in the block that is always guaranteed to contain a transition
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This feature is used to obtain block synchronization
Alignment Marker
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Composed of a specially defined 66-bit block with a control block sync header
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Not scrambled in order for the receiver to find alignment marker, deskew the
PCS lanes, and reassemble the aggregate stream before descramble
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Added after encoding and removed before decoding
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Inserted after every 16383 66-bit blocks on each PCS lane
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