Specific Tasks - VeEX MPA User Manual

MPA_e_manual_D07-00-129P_RevA00
BLKLOC
ALMARK
SYNCHDR
BIP8
Lane Summary

Specific Tasks

MLD Specific Tasks
This section includes tasks that are specific to the operation of the MLD protocol
processor.
For a description of specific screens and their functionality, refer to
Functions and Descriptions
The following Specific Tasks for this protocol processor are discussed:
Block Lock Loss. Indicates that one or more virtual lanes is
receiving a Loss of Block Lock alarm.
Alignment Mark. Indicates that one or more virtual lanes is
receiving any Alignment Mark errors.
Synchronization Header. Indicates that one or more virtual
lanes is receiving any Synchronization Header errors.
Bit Interleaved Parity 8. Indicates that one or more virtual
lanes is receiving any BIP 8 errors.
Lane Numbers/Positions. Shows the status of each Logical
or FEC/PCS virtual lane number, and the position number (in
parentheses) that the received virtual lane number was
assigned to.
Unframed BERT interfaces will just show the received
physical lane numbers.
A Green LED indicates error-free operation, whereas a Red
LED indicates a problem. Click on any Lane number to view
that lane's error/alarm summary statistics.
Overview.
MLD Tab
MLD - Screen
172