Samsung S3C6400X User Manual page 8

S3C6400
RISC MICROPROCESSOR
1.1.3 Memory Subsystem
The S3C6400 microprocessor provides the following Memory Subsystem features:
High bandwidth Memory Matrix subsystem
Two independent external memory ports (1 Static-DRAM Hybrid Memory port and 1 DRAM ports)
Matrix architecture increases overall bandwidth with the simultaneous access capability
1.1.3.1 Static-DRAM Hybrid Memory port configurable to support the following memory types:
Support SRAM/ROM/NOR Flash Interface
x8 or x16 data bus
o
Address range support: max. 26-bits (128MB)
o
Support byte and half-word access
o
OneNAND Flash interface
x16 data bus
o
NAND Flash Boot Loader
System can be booted from NAND when system initialization begins
o
Reset of memory area is used for storing user data
o
Supports both SLC and MLC NAND Flash memory
o
CF interface
Compatible with CF+ and CompactFlash Spec.(Rev 3.0)
o
SDRAM Interface
x16 data bus
o
1.8/ 2.5V interface voltage
o
Density support:
o
Mobile SDRAM Interface
x16 data bus with 133Mbps/pin data rate
o
133MHz address and command bus speed
o
1.8/ 2.5V interface voltage
o
Density support: up to 2Gb
o
Mobile SDRAM feature support:
o
Mobile DDR Interface
x16 data bus with 266Mbs/pin double data rate (DDR)
o
1.8/ 2.5V interface voltage
o
Density support: up to 2Gb
o
Memory Port0 : up to 1Gb
Memory Port1 : up to 2Gb
DS (Driver Strength Control)
TCSR (Temperature Compensated Self-Refresh Control)
PASR (Partial Array Self-Refresh Control)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW
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