Samsung S3C6400X User Manual page 14

S3C6400
RISC MICROPROCESSOR
1.1.14.2 A/D Converter and Touch Screen Interface
8-ch multiplexed ADC
Max. 500K samples/sec and 10-bit resolution
1.1.15 Storage Devices
The S3C6400 microprocessor provides the following Storage Devices features:
1.1.15.1 MMC/SD Host
Multimedia Card Protocol version 4.0 compatible
SD Memory Card Protocol version 1.0 compatible
128 words FIFO for Tx/Rx
DMA based or Interrupt based operation
1.1.16 System Peripherals
The S3C6400 microprocessor provides the following System Peripherals features:
1.1.16.1 DMA controller
4 General DMAs embedded.
2 master ports per DMA.
8-channel supported per each DMA; totally 32 channel is supported.
Supports memory to memory, peripheral to memory, memory to peripheral, and peripheral to peripheral
Burst transfer mode to enhance the transfer rate.
1.1.16.2 Vectored Interrupt Controller
Supports for 32 vectored IRQ interrupts
Fixed hardware interrupt priority levels
Programmable interrupt priority levels
Hardware interrupt priority level masking
IRQ and FIQ generation
Test registers
Raw interrupt status
Interrupt request status
Privileged mode support for restricted access
Support for ARM v6 processor VIC port in synchronous and asynchronous mode, enabling faster interrupt
servicing
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW
1-11