Samsung S3C6400X User Manual page 12

S3C6400
RISC MICROPROCESSOR
1.1.8.3 IIS-Bus Stereo DAC Interface
1-ch IIS-bus for the audio-codec interface
Optional DMA-based operation
Serial, 8/16-bit per channel data transfers
Supports IIS, MSB-justified and LSB-justified data format
Can operate in Master or Slave mode
Various bit clock frequency and codec clock frequency support
16,24,32,48 fs of bit clock frequency and 256,384,512,768 fs of codec clock frequency
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1.1.9 USB Support
The S3C6400 microprocessor provides the following USB Support features:
1.1.9.1 USB OTG 2.0 High Speed
Complies with the OTG specification Rev 1.0 supplement to the USB 2.0 protocol Rev2.0
Configures as OTG device only, USB 1.1 device, OTG mini host only, or USB 1.1 mini host
Supports high speed (480Mbps), full speed (12Mbps) and low-speed (1.5Mbps)
1.1.9.2 USB Host
2-port USB Host
Complies with OHCI Rev. 1.0
Compatible with the USB Specification version 1.1
Supports full speed up to 12Mbps
1.1.10 IrDA v1.1
The S3C6400 microprocessor provides the following IrDA v1.1 features:
Dedicated IrDA for v1.1 (1.152Mbps and 4 Mbps)
Supports FIR (4Mbps),
SIR (111.5kbps) mode is supported by the UART IrDA 1.0 block
Internal 64-byte Tx/Rx FIFO
1.1.11 Serial Communication
The S3C6400 microprocessor provides the following Serial Communication features:
1.1.11.1 UART
4-channel UART with DMA-based or interrupt-based operation
Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive
Supports external clock for the UART operation(UCLK)
Programmable baud rate
Supports IrDA 1.0 SIR (115.2Kbps) mode
Loop back mode for testing
Each channel has internal 64-byte Tx FIFO and 64-byte Rx FIFO
Non-integer clock divides in Baud clock generation
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW
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