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20.3.2
Programming/Erasing Interface Parameters
The programming/erasing interface parameters specify the operating frequency, storage place for
program data, programming destination address, and erase block and exchange the processing
result for the downloaded on-chip program. These parameters use the general registers of the CPU
(ER0 and ER1) or the on-chip RAM area. The initial value is undefined by a reset or in hardware
standby mode.
When download, initialization, or on-chip program is executed, registers of the CPU except for
R0L are stored. The return value of the processing result is written to R0L. Since the stack area is
used for storing the registers except for R0L, the stack area must be saved at the processing start.
(A maximum size of stack area to be used is 128 bytes.)
The programming/erasing interface parameters are used in the following four items.
1. Download control
2. Initialization before programming or erasing
3. Programming
4. Erasing
These items use different parameters. The correspondence table is shown in table 20.4.
A result of initialization, programming, or erasure processing is returned to the FPFR parameters.
However, the meaning of bits in FPFR varies in each processing. For details, see descriptions of
FPFR for each processing.
Rev. 1.00, 09/03, page 541 of 704
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