Programming/Erasing Interface Parameters; Table 17.4 Parameters And Target Modes - Renesas H8SX/1500 Series Hardware Manual

32-bit cisc microcomputer

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Section 17 Flash Memory (0.18-(m F-ZTAT Version)

Programming/Erasing Interface Parameters

The programming/erasing interface parameters specify the operating frequency, storage place for

program data, start address of programming destination, and erase block number, and exchanges

the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the

on-chip RAM area. The initial values of programming/erasing interface parameters are undefined

at a power-on reset or a transition to software standby mode.

Since registers of the CPU except for R0 are saved in the stack area during download of an on-

chip program, initialization, programming, or erasing, allocate the stack area before performing

these operations (the maximum stack size is 128 bytes). The return value of the processing result

is written in R0. The programming/erasing interface parameters are used in download control,

initialization before programming or erasing, programming, and erasing. Table 17.4 shows the

usable parameters and target modes. The meaning of the bits in the flash pass and fail result

parameter (FPFR) varies in initialization, programming, and erasure.

A single byte of the start address of the on-chip RAM specified by FTDAR

Download Control: The on-chip program is automatically downloaded by setting the SCO bit in

FCCS to 1. The on-chip RAM area to download the on-chip program is the 4-kbyte area starting

from the start address specified by FTDAR. Download is set by the programming/erasing interface

registers, and the download pass and fail result parameter (DPFR) indicates the return value.

Rev. 3.00 Mar. 14, 2006 Page 586 of 804

REJ09B0104-0300

Initialization

On-chip RAM*

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